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1. 发明授权

US07100141B1 Technology mapping technique for fracturable logic elements 有权
$Technology mapping technique for fracturable logic elements$
标题翻译：可分割逻辑元件的技术映射技术
公开(公告)号：US07100141B1
公开(公告)日：2006-08-29
申请号：US10745913
申请日：2003-12-23
申请人： Boris Ratchev , Yean-Yow Hwang , Bruce Pedersen
发明人： Boris Ratchev , Yean-Yow Hwang , Bruce Pedersen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A technique of minimizes circuit area on programmable logic with fracturable logic elements by using “balancing” in the technology mapping stage of the programmable logic computer-aided-design flow. A fracturable LE can be used for logic implementation in many ways, such as being used as one maximum-sized look-up table (LUT) or multiple smaller LUTs. One of more inputs of the multiple smaller LUTs may be shared. By balancing, this means mean that the technology mapping algorithm is tuned to use more small LUTs and fewer maximum-sized LUTs to implement the circuit. Although this is counterintuitive since the larger LUTs are more effective at absorbing gates, the technique achieves a smaller final circuit area by packing small LUTs into fracturable LEs.
摘要翻译：通过在可编程逻辑计算机辅助设计流程的技术映射阶段中使用“平衡”来最小化具有可分解逻辑元件的可编程逻辑电路面积的技术。可破碎的LE可以用于许多方式的逻辑实现，例如用作一个最大尺寸的查找表（LUT）或多个较小的LUT。可以共享多个较小LUT的更多输入中的一个。通过平衡，这意味着技术映射算法被调整为使用更小的LUT和更少的最大尺寸的LUT来实现电路。虽然这是违反直觉的，因为较大的LUT在吸收栅极方面更有效，但是该技术通过将小型LUT封装成可分裂的LE来实现较小的最终电路面积。

2. 发明授权

US07181703B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07181703B1
公开(公告)日：2007-02-20
申请号：US10625505
申请日：2003-07-22
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

3. 发明授权

US07080333B1 Verifying logic synthesizers 失效
标题翻译：验证逻辑合成器
公开(公告)号：US07080333B1
公开(公告)日：2006-07-18
申请号：US10286374
申请日：2002-10-31
申请人： Boris Ratchev , Mike Hutton , Gregg Baeckler
发明人： Boris Ratchev , Mike Hutton , Gregg Baeckler
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： Methods and code for verifying that modifications or improvements to a synthesizer algorithm do not introduce errors. Specifically, a number or VHDL or Verilog models are chosen. Two netlists are then synthesized from each modeled circuit, once using a unmodified or trusted synthesizer, and once using the modified or improved synthesizer. For each circuit, a set of input test vectors are generated. These vectors are somewhat random in nature, but modified or generated intelligently using knowledge about the circuit to be testing. For each circuit, each netlist is simulated, generating a set of output vectors. These output vectors are compared. If the output vectors match each other for each of the circuits tested, there is a high probability that the improved or modified synthesizer is not introducing new errors into the netlist.
摘要翻译：用于验证对合成器算法进行修改或改进的方法和代码不会引入错误。具体来说，选择一个或多个VHDL或Verilog模型。然后从每个建模的电路合成两个网表，一次使用未修改或可信的合成器，一次使用修改或改进的合成器。对于每个电路，生成一组输入测试向量。这些向量本质上是随机的，但是使用关于要测试的电路的知识来智能地修改或生成。对于每个电路，模拟每个网表，生成一组输出向量。比较这些输出向量。如果输出矢量对于所测试的每个电路彼此匹配，则改进或修改的合成器不会将新错误引入网表的概率很高。

4. 发明授权

US07594208B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07594208B1
公开(公告)日：2009-09-22
申请号：US11610392
申请日：2006-12-13
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

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