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51. 发明授权

US06703327B2 High-pressure anneal process for integrated circuits 失效
标题翻译：集成电路的高压退火工艺
公开(公告)号：US06703327B2
公开(公告)日：2004-03-09
申请号：US10128757
申请日：2002-06-13
申请人： Richard H. Lane , Phillip G. Wald
发明人： Richard H. Lane , Phillip G. Wald
IPC分类号： H01L2100
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/324 , H01L29/513 , H01L29/518 , Y10S438/904 , Y10S438/908
摘要： An improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.
摘要翻译：一种用于退火集成电路以修复制造损坏的改进方法。集成电路在其中存在包含氢的形成气体的加压密封室中退火。通过增加氢气到制造集成电路的材料的扩散速率，腔室的加压减小了最终退火步骤对总热暴露的贡献。理想地，除了氢气之外，形成气体还包含至少一种不与氢气反应的其它气体，例如氮气或氩气，从而降低爆炸危险。然而，集成电路可以仅包含保持在大于环境大气压的压力的氢气的环境中退火。

52. 发明申请

US20020139388A1 Methods for reducing contamination of semiconductor substrates 有权
标题翻译：减少半导体衬底污染的方法
公开(公告)号：US20020139388A1
公开(公告)日：2002-10-03
申请号：US09820690
申请日：2001-03-30
发明人： Robert Chebi , David Hemker
IPC分类号： C25F001/00 , C25F003/30 , C25F005/00 , B08B006/00 , B08B007/00
CPC分类号： H01L21/67115 , B08B7/0071 , H01L21/67028 , H01L21/67103 , H01L21/67109 , Y10S414/135 , Y10S414/136 , Y10S414/137 , Y10S414/138 , Y10S414/139 , Y10S414/14 , Y10S438/904 , Y10S438/913
摘要： Methods for reducing contamination of semiconductor substrates after processing are provided. The methods include heating the processed substrate to remove adsorbed chemical species from the substrate surface by thermal desorption. Thermal desorption can be performed either in-situ or ex-situ. The substrate can be heated by convection, conduction, and/or radiant heating. The substrate can also be heated by treating the surface of the processed substrate with an inert plasma during which treatment ions in the plasma bombard the substrate surface raising the temperature thereof. Thermal desorption can also be performed ex-situ by applying thermal energy to the substrate during transport of the substrate from the processing chamber and/or by transporting the substrate to a transport module (e.g., a load lock) or to a second processing chamber for heating. Thermal desorption during transport can be enhanced by purging an inert gas over the substrate surface.
摘要翻译：提供了减少处理后的半导体衬底污染的方法。所述方法包括加热经处理的基底以通过热解吸从基底表面除去吸附的化学物质。热解吸可以原位或非原位进行。可以通过对流，传导和/或辐射加热来加热衬底。也可以通过用惰性等离子体处理处理的基板的表面来加热基板，在惰性等离子体中处理等离子体中的离子轰击衬底表面，提高其温度。也可以通过在将衬底从处理室传送过程中向衬底施加热能和/或通过将衬底传送到传输模块（例如，装载锁）或第二处理室来进行热解吸，加热。通过在衬底表面上吹扫惰性气体可以提高运输过程中的热解吸。

53. 发明申请

US20020048864A1 Laser apparatus, laser annealing method, and manufacturing method of a semiconductor device 有权
标题翻译：激光装置，激光退火方法以及半导体装置的制造方法
公开(公告)号：US20020048864A1
公开(公告)日：2002-04-25
申请号：US09986743
申请日：2001-11-09
发明人： Shunpei Yamazaki , Hisashi Ohtani , Koichiro Tanaka , Kenji Kasahara , Ritsuko Kawasaki
IPC分类号： H01L021/00 , H01L021/84
CPC分类号： H01L21/02683 , H01L21/02422 , H01L21/02488 , H01L21/02532 , H01L21/02595 , H01L21/02691 , H01L21/2026 , H01L27/1285 , Y10S438/904
摘要： To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser light emitted therefrom is linearized to increase the throughput and to reduce the production cost as a whole. Further, both the front side and the back side of an amorphous semiconductor film is irradiated with such laser light to obtain the crystalline semiconductor film with a larger crystal grain size.
摘要翻译：为了提供一种激光装置和激光退火方法，通过该方法获得具有较大晶粒尺寸的结晶半导体膜并且其运行成本低。使用易于维护的固态激光器和耐久性高的激光器，并且从其发射的激光线性化，从而提高了生产量并降低了整体的生产成本。此外，用这样的激光照射非晶半导体膜的正面和背面，得到晶粒尺寸较大的结晶半导体膜。

54. 发明申请

US20020004292A1 Laser apparatus, laser annealing method, and manufacturing method of a semiconductor device 有权
公开(公告)号：US20020004292A1
公开(公告)日：2002-01-10
申请号：US09932935
申请日：2001-08-21
发明人： Shunpei Yamazaki , Hisashi Ohtani , Koichiro Tanaka , Kenji Kasahara , Ritsuko Kawasaki
IPC分类号： H01L021/20
CPC分类号： H01L21/02683 , H01L21/02422 , H01L21/02488 , H01L21/02532 , H01L21/02595 , H01L21/02691 , H01L21/2026 , H01L27/1285 , Y10S438/904
摘要： To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser light emitted therefrom is linearized to increase the throughput and to reduce the production cost as a whole. Further, both the front side and the back side of an amorphous semiconductor film is irradiated with such laser light to obtain the crystalline semiconductor film with a larger crystal grain size.

55. 发明授权

US6071552A Insitu formation of TiSi.sub.2 /TiN bi-layer structures using self-aligned nitridation treatment on underlying CVD-TiSi.sub.2 layer 有权
标题翻译：使用自对准氮化处理对下层CVD-TiSi2层的TiSi2 / TiN双层结构的内部形成
公开(公告)号：US6071552A
公开(公告)日：2000-06-06
申请号：US163381
申请日：1998-09-30
申请人： Tzu-Kun Ku
发明人： Tzu-Kun Ku
IPC分类号： C23C16/42 , H01L21/285 , H01L21/768 , B05D5/12
CPC分类号： H01L21/76855 , C23C16/42 , H01L21/28518 , H01L21/76843 , Y10S438/904 , Y10S438/909
摘要： The present invention provides a method of forming a contact structure comprised of: a silicon substrate, a titanium silicide layer, a barrier layer (i.e., TiN or TiNO), and a metal layer (e.g., Al or W). There are three embodiments of the invention for forming the titanium silicide layer and two embodiments for forming the barrier layer (TiN or TiNO). The first embodiment for forming a TiSix layer comprises three selective deposition steps with varying TiCl4: SiH4 ratios. After the TiSix contact layer is formed a barrier layer and a metal plug layer are formed thereover to form a contact structure. The method comprises forming a barrier layer 140 over the silicide contact layer 126; and forming a metal plug 160 over the TiN barrier layer 140. The metal plug 160 is composed of Al or W.
摘要翻译：本发明提供一种形成接触结构的方法，包括：硅衬底，硅化钛层，阻挡层（即TiN或TiNO）和金属层（例如Al或W）。用于形成硅化钛层的本发明的三个实施例和用于形成阻挡层（TiN或TiNO）的两个实施例。用于形成TiSix层的第一实施例包括具有不同TiCl 4 :SiH 4比率的三个选择性沉积步骤。在形成TiSix接触层之后，形成阻挡层和金属塞层以形成接触结构。该方法包括在硅化物接触层126上形成阻挡层140; 并在TiN阻挡层140上形成金属插塞160.金属插塞160由Al或W组成。

56. 发明授权

US5851847A Photonic device and process for fabricating the same 失效
公开(公告)号：US5851847A
公开(公告)日：1998-12-22
申请号：US872575
申请日：1997-06-10
申请人： Hideo Yamanaka
发明人： Hideo Yamanaka
IPC分类号： H01L23/28 , H01L21/56 , H01L23/02 , H01L23/29 , H01L23/31 , H01L27/14 , H01L31/02 , H01L31/0203 , H01L21/00
CPC分类号： H01L31/0203 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12041 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/3025 , Y10S438/904
摘要： A photonic device according to the present inventions obtained by resin molding a photonic element mounted on a base using a light-transmitting resin wherein the cured hardness of the light-transmitting resin is set at a value for optimally minimizing the adhesion of dust particles on the surface of the light-transmitting resin and the generation rate of internal cracks of the light-transmitting resin for a predetermined temperature change on the basis of the correlation between the two. A process for fabricating a photonic device according to the present invention comprises resin molding a photonic element by potting a light-transmitting resin having a predetermined viscosity, and applying a predetermined heat treatment for curing the resin to a final hardness after driving out the bubbles from the inside of the light-transmitting resin and for relaxing the curing shrinkage stress.

57. 发明授权

US5384477A CMOS latchup suppression by localized minority carrier lifetime reduction 失效
标题翻译：通过局部少数载流子寿命降低的CMOS闭锁抑制
公开(公告)号：US5384477A
公开(公告)日：1995-01-24
申请号：US28456
申请日：1993-03-09
申请人： Constantin Bulucea , Esin Dermirlioglu , Sheldon Aronowitz
发明人： Constantin Bulucea , Esin Dermirlioglu , Sheldon Aronowitz
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L27/0921 , Y10S148/023 , Y10S438/904 , Y10S438/917
摘要： A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior Which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.
摘要翻译：描述了抑制CMOS结构中的闭锁的独特方法。可以植入在硅中显示中等水平并满足局部作用和电相容性标准的原子物质，以抑制引起闭锁的寄生双极性行为。通过CMOS结构在有源MOS器件区域之外的临界寄生双极区域可以实现少数载流子寿命的降低。实现这一目标的一个方法是在源极/漏极掺杂剂被植入之前，使用源极/漏极掩模来局部注入少数载流子寿命衰减器（MCLR）。这允许MCLR在n沟道晶体管和p沟道晶体管的不同深度或者甚至不同的物种中被引入。实现这一目标的另一种方法是要求在隔离氧化，栅极氧化或活性阈值植入完成之前，在该过程中非常早地完成覆盖MCLR植入物。

58. 发明授权

US5343068A Integrated bipolar power device and a fast diode 失效
标题翻译：集成双极性功率器件和快速二极管
公开(公告)号：US5343068A
公开(公告)日：1994-08-30
申请号：US852310
申请日：1992-03-18
申请人： Ferruccio Frisina , Giuseppe Ferla
发明人： Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L29/73 , H01L21/22 , H01L21/322 , H01L21/331 , H01L21/8222 , H01L27/07 , H01L27/082 , H01L29/732 , H01L29/861 , H02L27/082 , H02L27/102 , H02L29/70
CPC分类号： H01L27/0761 , H01L21/221 , Y10S438/904
摘要： A bipolar power device and a fast diode are formed in a single chip of semiconductor material. The chip contains a first area having high minority carrier lifetimes in which the bipolar power device is formed. The bipolar power device is therefore capable of handling high current densities. At least one second area of the device is formed with reduced minority carrier lifetimes, with a fast diode being formed in this region.
摘要翻译：在单芯片半导体材料中形成双极功率器件和快速二极管。芯片包含形成双极型功率器件的少数载流子寿命的第一区域。因此，双极型功率器件能够处理高电流密度。器件的至少一个第二区域形成为具有减少的少数载流子寿命，其中在该区域中形成快速二极管。

59. 发明授权

US5190885A IGBT process to produce platinum lifetime control 失效
公开(公告)号：US5190885A
公开(公告)日：1993-03-02
申请号：US852932
申请日：1992-03-13
申请人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana
发明人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana
IPC分类号： H01L21/033 , H01L21/22 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/739 , H01L29/745 , H01L29/749 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/033 , H01L21/221 , H01L21/266 , H01L21/3065 , H01L29/0619 , H01L29/1095 , H01L29/408 , H01L29/41741 , H01L29/41766 , H01L29/6634 , H01L29/66545 , H01L29/7396 , H01L29/7455 , H01L29/749 , Y10S438/904 , Y10S438/917
摘要： For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non-polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si-H into the film.

60. 发明授权

US4777149A Method of manufacturing power MOSFET 失效
标题翻译：功率MOSFET的制造方法
公开(公告)号：US4777149A
公开(公告)日：1988-10-11
申请号：US136770
申请日：1987-12-22
申请人： Hirohito Tanabe , Yu Ohata , Kazuaki Suzuki , Yukiharu Miwa , Yoshihito Nakayama
发明人： Hirohito Tanabe , Yu Ohata , Kazuaki Suzuki , Yukiharu Miwa , Yoshihito Nakayama
IPC分类号： H01L21/336 , H01L29/167 , H01L29/78 , H01L21/383
CPC分类号： H01L29/66712 , H01L21/221 , H01L29/167 , H01L29/66734 , H01L29/7805 , H01L29/7813 , H01L29/4236 , H01L29/456 , Y10S438/904
摘要： In a power MOS FET and the method of manufacturing such FET, in which a material, such as platinum, having a small resistivity compensation effect is diffused as a lifetime killer into the vicinity of a PN diode junction formed by the drain region and the base region. The diffusion is made through an opening formed in a covering insulator layer. An example of the lifetime killer is platinum and the preferable temperature range for diffusing platinum is not higher than 900.degree.C.
摘要翻译：在功率MOS FET和制造这种FET的方法中，其中具有小电阻率补偿效应的诸如铂的材料作为寿命抑制剂扩散到由漏极区域和基极形成的PN二极管结附近地区。通过形成在覆盖绝缘体层中的开口进行扩散。寿命杀手的一个例子是铂，扩散铂的优选温度范围不高于900℃。

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