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1. 发明授权

US5528058A IGBT device with platinum lifetime control and reduced gaw 失效
标题翻译： IGBT器件具有铂寿命控制和减少的gaw
公开(公告)号：US5528058A
公开(公告)日：1996-06-18
申请号：US329974
申请日：1994-10-13
申请人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana , Dumitru Sdrulla
发明人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana , Dumitru Sdrulla
IPC分类号： H01L21/033 , H01L21/22 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/739 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/74 , H01L31/111
CPC分类号： H01L29/408 , H01L21/033 , H01L21/221 , H01L21/266 , H01L21/3065 , H01L29/0619 , H01L29/1095 , H01L29/41741 , H01L29/6634 , H01L29/7396 , H01L29/7455 , H01L29/749 , H01L29/7802 , H01L29/41766 , H01L29/66545
摘要： For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non-polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si--H into the film.
摘要翻译：对于IGBT，MCT等器件，衬底由P +，N +和N-层和PN扩散形成，以限定N层中的主体和源极区域以及上表面的MOS栅极通道。 N层的尺寸和掺杂（DIFFERENCE 1014 / cm3）以阻止反向偏置电压。 N +层厚度>20μm，掺杂低于DIFFERENCE 1017 / cm3，但高于N-掺杂，以增强输出阻抗，并降低高Vce条件下的增益。或者N +层形成为具有高（DIFFERENCE5μm）的高掺杂（> 1017 / cm3）层和厚（>20μm）DIFFERENCE 1016 / cm3掺杂的层。离子注入1013至1016 / cm2的铂剂量并扩散到硅中以实现寿命控制。栅极和源极触点以及主体和源极扩散具有互补锥形的数字化指状图案，以最小化电流拥挤和宽栅极总线以最小化信号延迟。在栅极焊盘和主栅极总线下面和边缘周围的P +掺杂不利于在源极端部处的宽间隔的体区域和凸起位置中的击穿条件。平行于栅极指的宽二级栅极总线具有P +掺杂的中心条和沿其长度间隔开的横向短路条。通过在沉积期间控制离子化的气体停留时间，硅烷分压和氧气比例来制备低磷PSG和氮化物或氧氮化物或氮氧化物或单独的氮氧化物的不可极化的PECVD钝化膜，以最小化Si-H到薄膜中的掺入。

2. 发明授权

US5283202A IGBT device with platinum lifetime control having gradient or profile tailored platinum diffusion regions 失效
标题翻译：具有铂寿命控制的IGBT器件具有定制的铂扩散区域的梯度或轮廓
公开(公告)号：US5283202A
公开(公告)日：1994-02-01
申请号：US945817
申请日：1992-09-15
申请人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana , Dumitra Scrulla
发明人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana , Dumitra Scrulla
IPC分类号： H01L21/033 , H01L21/22 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/739 , H01L29/745 , H01L29/749 , H01L29/78 , H01L21/00 , H01L21/02 , H01L21/265 , H01L21/467
CPC分类号： H01L29/408 , H01L21/033 , H01L21/221 , H01L21/266 , H01L21/3065 , H01L29/0619 , H01L29/1095 , H01L29/41741 , H01L29/6634 , H01L29/7396 , H01L29/7455 , H01L29/749 , H01L29/7802 , H01L29/41766 , H01L29/66545 , Y10S438/904 , Y10S438/917
摘要： For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non-polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si--H into the film.
摘要翻译：对于IGBT，MCT等器件，衬底由P +，N +和N-层和PN扩散形成，以限定N层中的主体和源极区域以及上表面的MOS门控通道。 N层的尺寸和掺杂（-1014 / cm3）以阻止反向偏置电压。 N +层厚度> 20（μm），掺杂低于-1017 / cm3，但高于N-掺杂，以增强输出阻抗，并降低高Vce条件下的增益。或者N +层由薄（-5（my）m）高掺杂（> 1017 / cm3）层和厚度为（> 20（μm））的-1016 / cm3掺杂层形成。离子注入1013至1016 / cm2的铂剂量并扩散到硅中以实现寿命控制。栅极和源极触点以及主体和源极扩散具有互补锥形的数字化指状图案，以最小化电流拥挤和宽栅极总线以最小化信号延迟。在栅极焊盘和主栅极总线下面和边缘周围的P +掺杂不利于在源极端部处的宽间隔的体区域和凸起位置中的击穿条件。平行于栅极指的宽二级栅极总线具有P +掺杂的中心条和沿其长度间隔开的横向短路条。通过在沉积期间控制离子化的气体停留时间，硅烷分压和氧气比例来制备低磷PSG和氮化物或氧氮化物或氮氧化物或单独的氮氧化物的不可极化的PECVD钝化膜，以最小化Si-H到薄膜中的掺入。

3. 发明授权

US5262336A IGBT process to produce platinum lifetime control 失效
标题翻译： IGBT工艺生产铂寿命控制
公开(公告)号：US5262336A
公开(公告)日：1993-11-16
申请号：US852932
申请日：1992-03-13
申请人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana
发明人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana
IPC分类号： H01L21/322 , H01L21/033 , H01L21/22 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L21/00 , H01L21/02 , H01L21/467
CPC分类号： H01L29/408 , H01L21/033 , H01L21/221 , H01L21/266 , H01L21/3065 , H01L29/0619 , H01L29/1095 , H01L29/41741 , H01L29/6634 , H01L29/7396 , H01L29/7455 , H01L29/749 , H01L29/7802 , H01L29/41766 , H01L29/66545 , H01L2924/0002
摘要： For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to .about.10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non-polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si-H into the film.

4. 发明授权

US5190885A IGBT process to produce platinum lifetime control 失效
公开(公告)号：US5190885A
公开(公告)日：1993-03-02
申请号：US852932
申请日：1992-03-13
申请人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana
发明人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana
IPC分类号： H01L21/033 , H01L21/22 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/739 , H01L29/745 , H01L29/749 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/033 , H01L21/221 , H01L21/266 , H01L21/3065 , H01L29/0619 , H01L29/1095 , H01L29/408 , H01L29/41741 , H01L29/41766 , H01L29/6634 , H01L29/66545 , H01L29/7396 , H01L29/7455 , H01L29/749 , Y10S438/904 , Y10S438/917
摘要： For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non-polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si-H into the film.

5. 发明授权

US5045903A Topographic pattern delineated power MOSFET with profile tailored recessed source 失效
标题翻译：地形图案划线功率MOSFET，带轮廓定制凹槽源
公开(公告)号：US5045903A
公开(公告)日：1991-09-03
申请号：US439101
申请日：1989-11-16
申请人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
发明人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
IPC分类号： H01L21/3065 , H01L21/336 , H01L29/417 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7396 , H01L21/3065 , H01L29/41741 , H01L29/7802 , H01L29/41766 , H01L29/66545
摘要： A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.
摘要翻译：多晶硅的掺杂剂不透明层沉积在上基板表面上的栅极氧化物上，以在器件的制造期间用作图案定义。它提供对连续的P和N掺杂步骤的控制，其用于在硅衬底内形成必要的操作结，并且在衬底上形成导电结构。在上硅表面中形成沟槽，并且在栅极氧化物层的顶部淀积栅极导电层时，淀积源极导电层以与源区电接触。使用新颖的O2-SF6等离子体蚀刻技术来调整沟槽侧壁的轮廓。在沉积导电材料之前，在图案限定器和栅极氧化物结构的侧面上形成氧化物侧壁间隔物。施加平面化层并用作掩模，用于选择性地去除沉积在氧化物间隔物上方的任何导电材料。在开沟期间氧化物上的多晶硅层厚度减小，使得沉积在间隔物上方的任何导电材料向上突出以便于去除过量的导电材料。侧壁间隔物可以单独地或与沟槽的轮廓定制组合来定尺寸，以控制源极区宽度（即寄生夹紧基底宽度）和源极导体与FET沟道的接近。通过在它们之间形成低电阻率层来增强源极导电层与源极区之间的电接触。

6. 发明授权

US5283201A High density power device fabrication process 失效
标题翻译：高密度功率器件制造工艺
公开(公告)号：US5283201A
公开(公告)日：1994-02-01
申请号：US927169
申请日：1992-08-07
申请人： Dah W. Tsang , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore O. Meyer
发明人： Dah W. Tsang , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore O. Meyer
IPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L21/00 , H01L21/02 , H01L21/265
CPC分类号： H01L21/3065 , H01L21/033 , H01L21/266 , H01L29/0619 , H01L29/1095 , H01L29/408 , H01L29/41741 , H01L29/6634 , H01L29/66348 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/41766 , H01L29/42368 , H01L29/511 , H01L29/66545
摘要： A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48). This area is doped to form a source layer (72) atop the body layer (26') and then trenched to form a second trench (80) having sidewalls aligned to the spacer inner surfaces. Second trench (80) defines vertically-oriented source and body layers (86, 90) stacked along gate oxide layer (60) to form vertical channels on opposite sides of second trench (80).
摘要翻译：在包括用于IGBT的P体层（26），N-漏极层（24）和可选的P +层（22）的衬底（20）上形成凹陷栅极功率MOSFET。形成在基板上表面（28）上的开沟保护层（30）被图案化以限定作为条纹或矩阵的暴露区域（46）和保护区域。具有内表面（48）的预定厚度（52）的侧壁间隔件（44）与保护层侧壁接触。第一沟槽（50）形成在具有与侧壁间隔物外表面（47）对准的侧壁并且通过P体层（26）的深度方向延伸至至少预定深度（56）的衬底区域（46）中。栅极氧化物（60）形成在沟槽壁上，栅极多晶硅（62）将沟槽重新填充到衬底上表面（28）附近的水平面（64）。侧壁间隔物（44）之间的氧化物（68）覆盖多晶硅（62）。去除保护层暴露间隔件内表面（48）之间的上基板表面（28'）。该区域被掺杂以在主体层（26'）顶部形成源极层（72），然后被沟槽以形成具有与间隔物内表面对准的侧壁的第二沟槽（80）。第二沟槽（80）限定垂直取向的源极和主体层（86,90），沿着栅极氧化物层（60）堆叠以在第二沟槽（80）的相对侧上形成垂直沟道。

7. 发明授权

US5019522A Method of making topographic pattern delineated power MOSFET with profile tailored recessed source 失效
标题翻译：使用轮廓定制凹槽源制作地形图案划线功率MOSFET的方法
公开(公告)号：US5019522A
公开(公告)日：1991-05-28
申请号：US460258
申请日：1990-01-02
申请人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
发明人： Theodore O. Meyer , John W. Mosier, II , Douglas A. Pike, Jr. , Theodore G. Hollinger , Dah W. Tsang
IPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L21/336 , H01L29/417 , H01L29/739 , H01L29/78
CPC分类号： H01L21/033 , H01L21/266 , H01L21/3065 , H01L29/41741 , H01L29/7396 , H01L29/7802 , H01L29/41766 , H01L29/66545
摘要： A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structure, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.
摘要翻译：多晶硅的掺杂剂不透明层沉积在上基板表面上的栅极氧化物上，以在器件的制造期间用作图案定义。它提供对连续的P和N掺杂步骤的控制，其用于在硅衬底内形成必要的操作结，并且在衬底上形成导电结构。在上硅表面中形成沟槽，并且在栅极氧化物层的顶部淀积栅极导电层时，淀积源极导电层以与源区电接触。使用新颖的O2-SF6等离子体蚀刻技术来调整沟槽侧壁的轮廓。在沉积导电材料之前，在图案定义器和栅极氧化物结构的侧面上形成氧化物侧壁间隔物。施加平面化层并用作掩模，用于选择性地去除沉积在氧化物间隔物上方的任何导电材料。在开沟期间氧化物上的多晶硅层厚度减小，使得沉积在间隔物上方的任何导电材料向上突出以便于去除过量的导电材料。侧壁间隔物可以单独地或与沟槽的轮廓定制组合来定尺寸，以控制源极区宽度（即寄生夹紧基底宽度）和源极导体与FET沟道的接近。通过在它们之间形成低电阻率层来增强源极导电层与源极区之间的电接触。

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