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1. 发明申请

US20110081759A1 POWER MOS ELECTRONIC DEVICE AND CORRESPONDING REALIZING METHOD 有权
公开(公告)号：US20110081759A1
公开(公告)日：2011-04-07
申请号：US12967845
申请日：2010-12-14
申请人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
发明人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L21/8232
CPC分类号： H01L29/7802 , H01L29/4238 , H01L29/4916 , H01L29/4933 , H01L29/4983
摘要： Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

2. 发明授权

US07569883B2 Switching-controlled power MOS electronic device 有权
标题翻译：开关控制功率MOS电子器件
公开(公告)号：US07569883B2
公开(公告)日：2009-08-04
申请号：US11285759
申请日：2005-11-21
申请人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magri , Antonio Giuseppe Grimaldi , Gaetano Bazzano
发明人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magri , Antonio Giuseppe Grimaldi , Gaetano Bazzano
IPC分类号： H01L29/76 , H01L29/94 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/4238 , H01L29/4916 , H01L29/4933 , H01L29/4983
摘要： Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least a connection layer arranged in series to at least one of said conductive strip. Such gate structure comprising at least a plurality of independent islands formed on the upper surface of the conductive strips and suitably formed on the connection layers. Said islands being realized with at least one second conductive material such as silicide.
摘要翻译：这种类型的功率电子MOS器件包括多个基本功率MOS晶体管和一个栅极结构，该栅极结构包括由第一导电材料（例如多晶硅），多个栅极指状物或连接到栅极焊盘的金属轨道至少一个与至少一个所述导电带串联布置的连接层。这种门结构包括形成在导电条的上表面上并适当地形成在连接层上的至少多个独立的岛。所述岛通过至少一种第二导电材料如硅化物实现。

3. 发明授权

US06468866B2 Single feature size MOS technology power device 有权
标题翻译：单功能尺寸MOS技术电源设备
公开(公告)号：US06468866B2
公开(公告)日：2002-10-22
申请号：US09427237
申请日：1999-10-26
申请人： Ferruccio Frisina , Angelo Magri , Giuseppe Ferla , Richard A. Blanchard
发明人： Ferruccio Frisina , Angelo Magri , Giuseppe Ferla , Richard A. Blanchard
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0847 , H01L29/0869 , H01L29/1095 , H01L29/66333
摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.
摘要翻译： MOS技术功率器件包括第一导电类型的半导体材料层，覆盖半导体材料层的导电绝缘栅极层和多个基本功能单元。导电绝缘栅层包括置于半导体材料层上方的第一绝缘材料层，位于第一绝缘材料层上方的导电材料层和置于导电材料层上方的第二绝缘材料层。每个基本功能单元包括形成在半导体材料层中的第二导电类型的细长体区域。每个基本功能单元还包括在细长体区域上方延伸的绝缘栅极层中的细长窗口。每个细长体区域包括掺杂有第一导电类型的掺杂剂的源区，插入有细长体区的一部分，其中不提供第一导电类型的掺杂剂。 MOS技术功率器件还包括多个绝缘材料侧壁间隔物，其沿着每个细长窗口的细长边缘设置在半导体材料层之上，以密封绝缘栅极层中每个细长窗口的边缘与设置在绝缘栅极上的源极金属层层和半导体材料层。源极金属层沿着细长主体区域的长度通过每个细长窗口接触每个体区域和每个源极区域。

4. 发明授权

US6064087A Single feature size MOS technology power device 失效
公开(公告)号：US6064087A
公开(公告)日：2000-05-16
申请号：US739466
申请日：1996-10-29
申请人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla
发明人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L29/74 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/749 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/66333 , H01L29/0696 , H01L29/1095 , H01L29/7802 , H01L29/0847
摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

5. 发明授权

US5841167A MOS-technology power device integrated structure 失效
公开(公告)号：US5841167A
公开(公告)日：1998-11-24
申请号：US772657
申请日：1996-12-23
申请人： Antonio Grimaldi , Antonino Schillaci , Ferruccio Frisina , Giuseppe Ferla
发明人： Antonio Grimaldi , Antonino Schillaci , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L21/336 , H01L23/482 , H01L29/06 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66712 , H01L23/4824 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/7802 , H01L29/41725 , H01L2924/0002
摘要： A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of bodystripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion. The body stripes are divided by the at least one first elongated stripe into at least two groups of body stripes, wherein one end of each body stripe is merged with the annular frame portion of the second conductivity type and the other end is merged with the at least one first elongated stripe. A conductive gate finger is insulatively disposed above the first elongated stripe and is part of the first web structure. A conductive gate ring surrounds the conductive gate layer and the conductive gate finger and completes the first web structure. A metal gate finger is disposed above the conductive gate finger and is merged at its ends with a metal gate ring structure disposed above the conductive gate ring to provide a third web structure. Source metal plates cover the at least two groups of body stripes and contact each source region and each body stripe to form a source electrode of the power device. A bottom surface of the semiconductor material layer forms a drain of the power device.

6. 发明授权

US5817546A Process of making a MOS-technology power device 失效
标题翻译：制造MOS技术电源设备的过程
公开(公告)号：US5817546A
公开(公告)日：1998-10-06
申请号：US576989
申请日：1995-12-19
申请人： Giuseppe Ferla , Ferruccio Frisina
发明人： Giuseppe Ferla , Ferruccio Frisina
IPC分类号： H01L21/336 , H01L29/10 , H01L21/332
CPC分类号： H01L29/66712 , H01L29/1095 , Y10S148/126
摘要： A process forms a MOS-technology power device including a semiconductor material layer of a first conductivity type and a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type. The process includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. A dopant of the second conductivity type is implanted twice at different concentrations and energies into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer. A dopant of the first conductivity type is then implanted into the heavily doped regions to form source regions substantially aligned with the edges of the insulated gate layer.
摘要翻译：一种工艺形成包括第一导电类型的半导体材料层和设置在其中的体区的MOS技术功率器件。身体区域包括第二导电类型的重掺杂区域，第二导电类型的轻掺杂区域和第一导电类型的重掺杂区域。该方法包括在半导体材料层的表面的部分上形成绝缘栅极层，以使半导体材料层的选定部分露出。将第二导电类型的掺杂剂以不同的浓度和能量注入到半导体材料层的选定区域中两次。注入的离子热扩散以形成体区，每个体区包括基本上与绝缘栅层的边缘对准的重掺杂区，以及通过第一掺杂剂在绝缘栅层下方的横向扩散形成的轻掺杂区。然后将第一导电类型的掺杂剂注入到重掺杂区域中以形成与绝缘栅极层的边缘基本对准的源极区域。

7. 发明授权

US5065213A Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process 失效
标题翻译：集成式高压双极型功率晶体管和低电压MOS功率晶体管结构在发光二极管开关配置和相关制造过程中
公开(公告)号：US5065213A
公开(公告)日：1991-11-12
申请号：US288405
申请日：1988-12-21
申请人： Ferruccio Frisina , Giuseppe Ferla
发明人： Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/07 , H01L29/739 , H01L29/78
CPC分类号： H01L27/0716 , Y10S148/009
摘要： A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor an a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N-epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus completely buried active sturcture. In the horizontal MOS version, in a N-epitaxial layer there are two P+regions, the first, which constitutes the base of the bipolar transistor, receives the N+emitter region of the same transistor; the second receives two N+regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

8. 发明授权

US08624332B2 Vertical conduction power electronic device and corresponding realization method 有权
标题翻译：垂直传导功率电子器件及相应的实现方法
公开(公告)号：US08624332B2
公开(公告)日：2014-01-07
申请号：US11235495
申请日：2005-09-26
申请人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magrì
发明人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magrì
IPC分类号： H01L27/088
CPC分类号： H01L29/66666 , H01L21/26586 , H01L29/0692 , H01L29/0696 , H01L29/0878 , H01L29/417 , H01L29/41708 , H01L29/41716 , H01L29/41741 , H01L29/41766 , H01L29/66128 , H01L29/66272 , H01L29/66333 , H01L29/66712 , H01L29/7322 , H01L29/7398 , H01L29/7809 , H01L29/8611
摘要： A vertical conduction electronic power device includes respective gate, source and drain areas in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be formed by a first metallization level. Corresponding gate, source and drain terminals or pads may be formed by a second metallization level. The power device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area. The modular areas are separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge.
摘要翻译：垂直导电电子功率器件包括布置在半导体衬底上的外延层中的相应栅极，源极和漏极区域。相应的栅极，源极和漏极金属化可以由第一金属化层形成。相应的栅极，源极和漏极端子或焊盘可以由第二金属化层形成。功率器件被配置为彼此平行延伸的一组模块化区域，每个模块区域具有由狭窄栅极区域周边包围的矩形细长源区域。模块化区域通过区域彼此分离，其中漏区域平行延伸并且在其相对端连接到第二闭合区域，其中漏区域形成装置外围边缘。

9. 发明授权

US07875936B2 Power MOS electronic device and corresponding realizing method 有权
标题翻译：功率MOS电子器件及相应的实现方法
公开(公告)号：US07875936B2
公开(公告)日：2011-01-25
申请号：US11285741
申请日：2005-11-21
申请人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
发明人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L27/088
CPC分类号： H01L29/7802 , H01L29/4238 , H01L29/4916 , H01L29/4933 , H01L29/4983
摘要： Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.
摘要翻译：该功率MOS器件包括具有相应栅极结构的多个基本功率MOS晶体管，并且包括具有厚度中心部分和厚度减小的侧部的双重厚度的栅极氧化物。这种具有栅极结构的器件包括第一栅极导电部分，该第一栅极导电部分重叠在所述减小厚度的横向部分上，以便为基本MOS晶体管限定栅电极以及导电结构或网状物。这种导电结构包括多个第二导电部分，其重叠在栅极氧化物的厚的中心部分上并且通过多个导电桥彼此互连并连接到第一栅极导电部分。

10. 发明授权

US06756259B2 Gate insulating structure for power devices, and related manufacturing process 有权
标题翻译：功率器件门绝缘结构及相关制造工艺
公开(公告)号：US06756259B2
公开(公告)日：2004-06-29
申请号：US10061606
申请日：2002-02-01
申请人： Ferruccio Frisina , Giuseppe Ferla
发明人： Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L218238
CPC分类号： H01L29/7802 , G11C29/14 , G11C29/50 , G11C2029/0403 , H01L21/76202 , H01L21/8238 , H01L29/6656 , H01L29/66712
摘要： Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.
摘要翻译：半导体功率器件包括第一导电类型的半导体层，其中形成包括第一导电类型的源极区的第二导电类型的体区，与半导体层重叠的栅极氧化层，主体区域，叠加到栅极氧化物层的多晶硅区域和叠加到多晶硅区域的第一绝缘材料的区域。该器件包括位于两个多晶硅区域和第一绝缘材料的区域的一侧上的第二绝缘材料的区域，以及位于主体区域上的开口附近的栅极氧化物层的区域，位于多晶硅区域之间的氧化物区域以及第二绝缘材料的区域，叠加到第二绝缘材料的区域的氧化物间隔物。

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