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51. 发明授权

US06667199B2 Semiconductor device having a replacement gate type field effect transistor and its manufacturing method 失效
标题翻译：具有替代栅极型场效应晶体管的半导体器件及其制造方法
公开(公告)号：US06667199B2
公开(公告)日：2003-12-23
申请号：US10081227
申请日：2002-02-25
申请人： Kazuyoshi Torii , Ryuta Tsuchiya , Masatada Horiuchi , Takahiro Onai
发明人： Kazuyoshi Torii , Ryuta Tsuchiya , Masatada Horiuchi , Takahiro Onai
IPC分类号： H01L21338
CPC分类号： H01L29/66545 , H01L21/823425 , H01L21/82345
摘要： The present invention provides a MISFET with a replacement gate electrode, which ensures large ON-current. A semiconductor device, in which on the substrate, first and second field effect transistors are formed, the first field effect transistor is a replacement gate type field effect transistor, and the length of the overlap between a gate electrode and a source/drain diffusion zone of the first field effect transistor correspond to that between a gate electrode and a source/drain diffusion zone of the second field effect transistor.
摘要翻译：本发明提供了具有替代栅电极的MISFET，其确保大的导通电流。一种其中在衬底上形成第一和第二场效应晶体管的半导体器件，第一场效应晶体管是替代栅极型场效应并且第一场效应晶体管的栅极电极和源极/漏极扩散区域之间的重叠的长度对应于第二场效应晶体管的栅极电极和源极/漏极扩散区域之间的重叠长度。

52. 发明授权

US06338994B1 Semiconductor device and method of fabricating thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06338994B1
公开(公告)日：2002-01-15
申请号：US09475033
申请日：1999-12-30
申请人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
发明人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L27/10852
摘要： A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.
摘要翻译：一种形成在半导体衬底上的具有底电极，铁电体膜和顶电极的半导体器件，其中，强电介质膜的每个主横截面相对于半导体衬底的主表面的角度小于75 度。如果用单一光刻工艺步骤蚀刻上电极，铁电体膜和底电极，则将铁电膜形成具有这种角度的横截面中的梯形，提供了在顶电极和底电极之间没有电短路的微电容器。该新技术实现了适用于高度集成的存储器件的微观存储单元结构。

53. 发明授权

US5811316A Method of forming teos oxide and silicon nitride passivation layer on aluminum wiring 失效
标题翻译：在铝线上形成氧化硅和氮化硅钝化层的方法
公开(公告)号：US5811316A
公开(公告)日：1998-09-22
申请号：US460931
申请日：1995-06-05
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/28
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

54. 发明授权

US5331191A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US5331191A
公开(公告)日：1994-07-19
申请号：US954142
申请日：1992-09-30
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/10
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区和非活性区域的全部表面部分中的方式，在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

55. 发明授权

US5270232A Process for fabricating field effect transistor 失效
标题翻译：制造场效应晶体管的工艺
公开(公告)号：US5270232A
公开(公告)日：1993-12-14
申请号：US943018
申请日：1992-09-10
申请人： Shinichiro Kimura , Shoji Shukuri , Hiromasa Noda , Digh Hisamoto , Hideyuki Matsuoka , Kazuyoshi Torii , Natsuki Yokoyama , Toshiyuki Yoshimura , Kazunori Tsujimoto , Eiji Takeda
发明人： Shinichiro Kimura , Shoji Shukuri , Hiromasa Noda , Digh Hisamoto , Hideyuki Matsuoka , Kazuyoshi Torii , Natsuki Yokoyama , Toshiyuki Yoshimura , Kazunori Tsujimoto , Eiji Takeda
IPC分类号： H01L29/78 , H01L21/285 , H01L21/336 , H01L21/70
CPC分类号： H01L29/66606 , H01L21/28525 , H01L29/66621 , Y10S438/947
摘要： A very thin oxide film is formed at an opening formed in an insulator film and a conductor layer, on a substrate, and impurity-containing polysilicon is formed on the sidewall of the opening. Impurity diffusion from the from the silicon into the substrate through the very thin oxide film causes a lowering in effective concentration of the diffused impurities, resulting in the formation of shallower source/drain region. Thereafter, a gate insulator film and a gate electrode are formed on the substrate surface in an area bounded by an insulator film formed on the sidewall of the opening. The gate electrode smaller than the opening, the size of which corresponds to the limit of processing, and the shallower source/drain region afford a miniaturized MOSFET.
摘要翻译：在基板上形成绝缘体膜和导体层的开口处形成非常薄的氧化膜，并且在开口的侧壁上形成含杂质的多晶硅。通过非常薄的氧化膜从硅到衬底的杂质扩散导致扩散杂质的有效浓度降低，导致形成较浅的源/漏区。此后，在由形成在开口的侧壁上的绝缘膜限定的区域中的基板表面上形成栅绝缘膜和栅电极。小于开口的栅极电极，其尺寸对应于处理极限，并且较浅的源极/漏极区域提供小型化的MOSFET。

56. 发明授权

US08638029B2 Spark plug for internal combustion engine and method of manufacturing the spark plug 有权
标题翻译：用于内燃机的火花塞和制造火花塞的方法
公开(公告)号：US08638029B2
公开(公告)日：2014-01-28
申请号：US13641611
申请日：2011-04-15
申请人： Kazuyoshi Torii , Akira Suzuki , Mamoru Musasa
发明人： Kazuyoshi Torii , Akira Suzuki , Mamoru Musasa
IPC分类号： H01T13/20
CPC分类号： H01T13/39 , H01T13/32 , H01T21/02
摘要： A spark plug includes a center electrode, a ground electrode, and a noble metal tip. The noble metal tip is joined to an object member of at least one of two electrodes via a fusion zone. A projected overlap region of the noble metal tip and the fusion zone accounts for 70% or more of a projected region of the noble metal tip. The object member contains at least Si out of Al and Si such that the amount of Si is 0.4% by mass or higher and such that the total amount of Al and Si is 0.5% by mass. Multi-fusion spots exist on the surface of the fusion zone. Segments of a baseline which pass through the respective multi-fusion spots have a total length of a predetermined percentage of the length of the baseline. Joining strength to the noble metal tip can thereby be greatly improved when the member to be joined contains Si.
摘要翻译：火花塞包括中心电极，接地电极和贵金属电极头。贵金属端头通过熔融区域与两个电极中的至少一个的目标构件接合。贵金属端头和熔融区域的突出重叠区域占贵金属电极头的投影区域的70％以上。目标构件至少包含Al和Si中的Si，使得Si的量为0.4质量％以上，并且使Al和Si的总量为0.5质量％。融合区表面存在多个融合点。通过相应的多融合点的基线段具有基线长度的预定百分比的总长度。因此，当待接合部件含有Si时，能够大大提高与贵金属电极头的接合强度。

57. 发明授权

US08476817B2 Spark plug 有权
标题翻译：火花塞
公开(公告)号：US08476817B2
公开(公告)日：2013-07-02
申请号：US13146816
申请日：2010-01-27
申请人： Naomichi Miyashita , Mamoru Musasa , Akira Suzuki , Kazuyoshi Torii , Tomoaki Kato
发明人： Naomichi Miyashita , Mamoru Musasa , Akira Suzuki , Kazuyoshi Torii , Tomoaki Kato
IPC分类号： H01T13/20
CPC分类号： H01T13/39 , H01T13/32
摘要： The present invention provides a spark plug which is capable of suppressing a occurrence of crack and separation by determining a structural configuration of a melting portion formed in a junction portion between a discharge portion and a pedestal portion which form an ignition portion that protrudes from a ground electrode. In a profile line shape of a cross section including a center axis P of an ignition portion 80, an exposure surface 88 of a melting portion 83 connects a side surface 82 of a discharge portion 81 and a side surface 85 of a pedestal portion 84. Further, an exterior angle θ formed between an imaginary line Q, which passes through a boundary position X1 between the melting portion 83 and the pedestal portion 84 and a boundary position X2 between the melting portion 83 and the discharge portion 81, and the center axis P at a node C, satisfies 135°≦θ≦175°. Furthermore, a proportion T/S of a forming depth T of the melting portion 83 to an outside diameter S of the discharge portion 81 satisfies T/S≧0.5.
摘要翻译：本发明提供一种火花塞，其能够通过确定在形成从地面突出的点火部的排出部和基座部之间的接合部中形成的熔融部的结构构造来抑制裂纹和分离的发生电极。在包括点火部分80的中心轴线P的截面的轮廓线形状中，熔化部分83的暴露表面88连接排出部分81的侧表面82和基座部分84的侧表面85。此外，在通过熔融部83和基座部84之间的边界位置X1的虚拟线Q与熔化部83与排出部81之间的边界位置X2之间形成的外角θ和中心轴 P在节点C处满足135°@ @ @ 175°。此外，熔融部83的成形深度T与排出部81的外径S的比例T / S满足T /S≥0.5。

58. 发明授权

US08410673B2 Spark plug having a ground electrode of specific alloy composition to which a noble metal tip is joined 有权
标题翻译：具有接合有贵金属电极头的特定合金组成的接地电极的火花塞
公开(公告)号：US08410673B2
公开(公告)日：2013-04-02
申请号：US13062571
申请日：2009-09-09
申请人： Kazuyoshi Torii , Tomoo Tanaka , Akira Suzuki , Mamoru Musasa , Naomichi Miyashita , Osamu Yoshimoto
发明人： Kazuyoshi Torii , Tomoo Tanaka , Akira Suzuki , Mamoru Musasa , Naomichi Miyashita , Osamu Yoshimoto
IPC分类号： H01T13/28
CPC分类号： H01T13/39 , B23K35/322 , C22C5/04 , C22C19/058
摘要： A spark plug having a center electrode and a ground electrode including a ground electrode main body part having an end thereof facing the center electrode and a noble metal tip joined to the ground electrode main body part at a position facing a leading end of the center electrode, a spark discharge gap being formed between the leading end of the center electrode and the noble metal tip, wherein at least a portion of the ground electrode main body part, to which the noble metal tip is joined, is made of an Ni alloy containing 12 to 45 mass % of Cr, 7 mass % or less of Fe, 0.5 to 5 mass % of Al, 0.3 to 5 mass % of Si and 50 mass % or more of the balance, and wherein the joined portion and the noble metal tip are joined by laser welding or electron beam welding.
摘要翻译：一种火花塞，其具有中心电极和接地电极，该火花塞具有接地电极主体部分，该接地电极主体部分的端部面向中心电极;以及贵金属电极头，其在面向中心电极前端的位置处接合到接地电极主体部分在中心电极的前端和贵金属电极头之间形成有火花放电间隙，其中与贵金属电极头接合的接地电极主体部分的至少一部分由含有 12〜45质量％的Cr，7质量％以下的Fe，0.5〜5质量％的Al，0.3〜5质量％的Si和50质量％以上的余量，其中，接合部和贵金属尖端通过激光焊接或电子束焊接连接。

59. 发明授权

US08378560B2 Spark plug 有权
标题翻译：火花塞
公开(公告)号：US08378560B2
公开(公告)日：2013-02-19
申请号：US12743022
申请日：2008-11-14
申请人： Akira Suzuki , Naomichi Miyashita , Kazuyoshi Torii
发明人： Akira Suzuki , Naomichi Miyashita , Kazuyoshi Torii
IPC分类号： H01T13/20
CPC分类号： H01T13/39 , C22C5/04
摘要： An ignition part (80) of a ground electrode (30) includes a fused part (85) in which construction materials of a base portion (82) and a noble metal member (81) are fused and mixed by performing laser welding on the two. In the fused part (85), an average ratio P of components originated from the noble metal member (81) at points K1, L1, and M1 is equal to or greater than 80%, and an average ratio Q of components originated from the base portion at points K3, L3, and M3 is equal to or higher than 20%, and P+Q is equal to or higher than 160%. Accordingly, it is possible to obtain joining strength in the parts in the ignition part (80), thereby sufficiently preventing the generation of cracks, separation, and the like due to thermal stress.
摘要翻译：接地电极（30）的点火部（80）包括：熔融部（85），其中基部（82）和贵金属部件（81）的构造材料通过在两者上进行激光焊接而熔融混合。在熔融部（85）中，在点K1，L1，M1处，来自贵金属构件（81）的成分的平均比例P为80％以上，来自点K3，L3，M3处的基极部分等于或高于20％，P + Q等于或高于160％。因此，可以获得点火部（80）的各部分的接合强度，从而充分防止由于热应力而产生裂纹，分离等。

60. 发明授权

US08294344B2 Spark plug and weld metal zone 有权
标题翻译：火花塞和焊缝金属带
公开(公告)号：US08294344B2
公开(公告)日：2012-10-23
申请号：US12810767
申请日：2008-12-25
申请人： Kazuyoshi Torii , Akira Suzuki , Naomichi Miyashita , Mamoru Musasa , Kenji Moritani
发明人： Kazuyoshi Torii , Akira Suzuki , Naomichi Miyashita , Mamoru Musasa , Kenji Moritani
IPC分类号： H01T13/20
CPC分类号： H01T13/39
摘要： A spark member (70) is formed by joining a noble metal member (71) and an intermediate member (75) and is provided in a spark discharge gap between a center electrode and a ground electrode (30). A bottom surface (80) of the intermediate member (75) is resistance-welded to an inner surface (33) of the ground electrode (30), and a weld metal zone (73) is formed in the region of joint therebetween. As viewed on the section of the spark member (70) which contains a centerline (Q), the weld metal zone (73) is reliably formed within the range of the length (D) of a columnar portion (76) as measured along a direction orthogonal to the projecting direction of the spark member (70) and has a length (d) of at least 0.1 times (10% of) the length (D).
摘要翻译：通过将贵金属构件（71）和中间构件（75）接合而形成火花构件（70），并且设置在中心电极和接地电极（30）之间的火花放电间隙中。中间构件（75）的底表面（80）被电阻焊接到接地电极（30）的内表面（33），并且在它们之间的接合区域中形成焊接金属区域（73）。如在包含中心线（Q）的火花部件（70）的部分观察的，焊接金属区域（73）可以沿着沿着柱状部分（76）的长度（D）的范围被可靠地形成，具有与火花部件（70）的突出方向垂直的方向，并且长度（d）为长度（D）的至少0.1倍（10％）。

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