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1. 发明申请

US20120097533A1 DOUBLE-LAYER SHUTTER SPUTTERING APPARATUS 有权
标题翻译：双层快门飞溅设备
公开(公告)号：US20120097533A1
公开(公告)日：2012-04-26
申请号：US13316927
申请日：2011-12-12
申请人： Shuji NOMURA , Ayumu Miyoshi , Hiroshi Miki
发明人： Shuji NOMURA , Ayumu Miyoshi , Hiroshi Miki
IPC分类号： C23C14/34
CPC分类号： C23C14/3464
摘要： A sputtering apparatus including a target holder configured to hold at least two targets; a substrate holder configured to hold a substrate; a first shutter plate arranged between the target holder and the substrate holder, the first shutter plate having at least two holes and being capable of rotating around an axis; a second shutter plate arranged between the first shutter plate and the substrate holder, the second shutter plate having at least two holes and being capable of rotating around the axis; wherein the first and second shutter plates are rotated such that paths are simultaneously created between the at least two targets and the substrate through the at least two holes of the rotated first shutter plate and the at least two holes of the rotated second shutter plate, and a film is formed on the substrate by co-sputtering of the at least two targets.
摘要翻译：一种溅射装置，包括被配置为保持至少两个靶的目标支架; 衬底保持器，其构造成保持衬底; 布置在所述目标保持器和所述基板保持器之间的第一挡板，所述第一挡板具有至少两个孔并且能够绕轴线旋转; 布置在所述第一活门板和所述衬底支架之间的第二活门板，所述第二活门板具有至少两个孔并能绕所述轴线旋转; 其中所述第一和第二快门板旋转，使得通过旋转的第一快门板的至少两个孔和旋转的第二快门板的至少两个孔同时在至少两个目标和基板之间产生通路，以及通过共溅射至少两个靶，在衬底上形成膜。

2. 发明申请

US20070228427A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070228427A1
公开(公告)日：2007-10-04
申请号：US11723683
申请日：2007-03-21
申请人： Yuichi Matsui , Hiroshi Miki
发明人： Yuichi Matsui , Hiroshi Miki
IPC分类号： H01L29/76
CPC分类号： H01L27/10852 , H01L21/02175 , H01L21/022 , H01L21/02271 , H01L21/31641 , H01L21/31645 , H01L27/10814 , H01L27/10894 , H01L28/91
摘要： HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.
摘要翻译：目前正在开发用于85nm技术节点DRAM中的电容器电介质膜的HfO 2膜和ZrO 2膜。然而，这些膜将难以在65nm技术节点或之后的DRAM中使用，因为它们的相对介电常数只有20-25。这些膜的介电常数可以通过稳定它们的立方相来增加。然而，这导致沿着晶粒边界的漏电流的增加，这使得难以将这些膜用作电容器电介质膜。为了克服这个问题，本发明将HfO 2 2或ZrO 2 2的基材与具有大离子半径的元素的氧化物如Y或La掺杂，以增加基材的氧配位数，从而即使当基材处于非晶状态时，其相对介电常数也提高到30以上。因此，本发明提供可用于形成满足65nm技术节点或更高版本的DRAM电容器的电介质膜。

3. 发明授权

US07034355B2 Nonvolatile semiconductor storage and its manufacturing method 有权
标题翻译：非易失性半导体存储及其制造方法
公开(公告)号：US07034355B2
公开(公告)日：2006-04-25
申请号：US10496000
申请日：2002-12-02
申请人： Hiroshi Miki
发明人： Hiroshi Miki
IPC分类号： H01L29/76
CPC分类号： H01L21/28211 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/511
摘要： To achieve a higher operating speed, higher reliability, and lower power consumption by reducing the thickness of an inter-poly silicon insulator film between a floating gate and a control gate of a flash memory, a silicon dioxide film, a silicon nitride film, tantalum pentoxide, and a silicon dioxide film are formed in a multilayer structure to serve as the inter-poly insulator film between a floating gate and a control gate. With this configuration, tantalum pentoxide formed on the silicon nitride film has a dielectric constant of 50 or more, which is higher than that of the silicon dioxide film, and the thickness of the inter-poly silicon insulator film can be reduced.
摘要翻译：为了通过减小浮动栅极和闪速存储器的控制栅极之间的多晶硅绝缘膜的厚度来实现更高的操作速度，更高的可靠性和更低的功率消耗，二氧化硅膜，氮化硅膜，钽五氧化物和二氧化硅膜形成为多层结构，以用作浮置栅极和控制栅极之间的多晶硅绝缘膜。利用这种构造，形成在氮化硅膜上的五氧化二钽的介电常数为50以上，高于二氧化硅膜的介电常数，能够降低多晶硅绝缘膜的厚度。

4. 发明授权

US06822276B1 Memory structure with a ferroelectric capacitor 失效
标题翻译：具有铁电电容的存储器结构
公开(公告)号：US06822276B1
公开(公告)日：2004-11-23
申请号：US09391250
申请日：1999-09-07
申请人： Kazuyoshi Torii , Hiroshi Miki , Yoshihisa Fujisaki
发明人： Kazuyoshi Torii , Hiroshi Miki , Yoshihisa Fujisaki
IPC分类号： H01L27108
CPC分类号： H01L28/56 , H01L21/28568 , H01L27/10852 , H01L27/10855 , H01L28/55 , H01L28/75
摘要： It is an object of the present invention to provide a fine memory cell structure preventing a reaction between an interlayer insulating film and a ferroelectric film and suitable for high integration. According to the invention, there is provided a structure in which a reaction barrier film 43 is interposed between a ferroelectric film 71 and an interlayer insulating film 32 and side walls of a diffusion barrier film 51 are not brought into direct contact with the ferroelectric film 71. Thereby, the reaction between the interlayer insulating film 32 and the ferroelectric film 71 can be restrained and exfoliation of the ferroelectric film 71 can be prevented.
摘要翻译：本发明的目的是提供一种防止层间绝缘膜和铁电体膜之间的反应并且适合于高集成度的精细存储单元结构。根据本发明，提供一种结构，其中反应阻挡膜43介于铁电膜71和层间绝缘膜32之间，并且扩散阻挡膜51的侧壁不与铁电体膜71直接接触由此，能够抑制层间绝缘膜32与强电介质膜71的反应，能够防止铁电体膜71的剥离。

5. 发明授权

US06800889B2 Semiconductor device and fabrication method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06800889B2
公开(公告)日：2004-10-05
申请号：US10073240
申请日：2002-02-13
申请人： Shinichiro Takatani , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Kazuyoshi Torii
发明人： Shinichiro Takatani , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Kazuyoshi Torii
IPC分类号： H01L2976
CPC分类号： H01L28/55 , H01L28/60
摘要： A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.
摘要翻译：半导体器件包括随后堆叠的具有下电极（102），高介电常数或铁电薄膜（103）和上电极（104）的电容器。具有抑制构成电极的金属或导电氧化物的催化活性的作用的杂质被添加到上电极（104）。杂质的添加对于防止在形成上电极（104）之后进行的氢热处理等电容的减少，绝缘失效以及电极的剥离等不良情况是有效的，长期可靠性。

6. 发明授权

US06509246B2 Production of semiconductor integrated circuit 失效
公开(公告)号：US06509246B2
公开(公告)日：2003-01-21
申请号：US09877207
申请日：2001-06-11
申请人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
发明人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
IPC分类号： H01L2120
CPC分类号： H01L28/84 , H01L27/10814 , H01L28/91
摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.

7. 发明授权

US06462368B2 Ferroelectric capacitor with a self-aligned diffusion barrier 失效
标题翻译：具有自对准扩散阻挡层的铁电电容器
公开(公告)号：US06462368B2
公开(公告)日：2002-10-08
申请号：US10059256
申请日：2002-01-31
申请人： Kazuyoshi Torii , Yasuhiro Shimamoto , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki
发明人： Kazuyoshi Torii , Yasuhiro Shimamoto , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki
IPC分类号： H01L2976
CPC分类号： H01L27/10855 , H01L21/76885 , H01L27/10894 , H01L28/91
摘要： A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layer of a switching transistor is self-aligned. As a result, side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.
摘要翻译：在下电极的底表面和将下电极连接到开关晶体管的扩散层之一的互连之间延伸的扩散防止层是自对准的。结果，由于通过使用虚拟膜形成孔图案，所以制造侧沟槽，并且即使存储部分的接触插塞与扩散防止层不对准，接触插塞也不与电介质膜直接接触具有很高的介电常数。因此，可以获得高度可靠的装置。

8. 发明授权

US06338994B1 Semiconductor device and method of fabricating thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06338994B1
公开(公告)日：2002-01-15
申请号：US09475033
申请日：1999-12-30
申请人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
发明人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L27/10852
摘要： A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.
摘要翻译：一种形成在半导体衬底上的具有底电极，铁电体膜和顶电极的半导体器件，其中，强电介质膜的每个主横截面相对于半导体衬底的主表面的角度小于75 度。如果用单一光刻工艺步骤蚀刻上电极，铁电体膜和底电极，则将铁电膜形成具有这种角度的横截面中的梯形，提供了在顶电极和底电极之间没有电短路的微电容器。该新技术实现了适用于高度集成的存储器件的微观存储单元结构。

9. 发明授权

US6055171A AC/DC converting circuit 失效
标题翻译： AC / DC转换电路
公开(公告)号：US6055171A
公开(公告)日：2000-04-25
申请号：US323568
申请日：1999-06-01
申请人： Shinichi Ishii , Hiroshi Miki
发明人： Shinichi Ishii , Hiroshi Miki
IPC分类号： H02J1/00 , H02M1/00 , H02M1/42 , H02M7/12 , H02M7/217 , H02M5/42
CPC分类号： H02M1/4208 , H02M1/4233 , H02M7/217 , Y02B70/126
摘要： An ac/dc converting circuit adapted to output a direct voltage that is higher than a full wave rectified voltage of an alternating input voltage is provided which includes an alternating current filter, and a condenser with a positive electrode and a negative electrode coupled to a dc output side of a full wave rectifying circuit. The full wave rectifying circuit includes a switching portion having upper and lower arms each having a semiconductor rectifying element and a self-commutated semiconductor switching element, and a rectifying portion having upper and lower arms each having a semiconductor rectifying element. The semiconductor rectifying elements in the upper arms of the full wave rectifying circuit has a common cathode coupled to the positive electrode, and the semiconductor rectifying elements in the lower arms has a common anode coupled to the negative electrode. The ac/dc converting circuit further includes a resistor provided between a coupling point of the rectifying elements of the upper arms of the full wave rectifying circuit and the negative electrode. In operation, a signal for controlling an ON/OFF state of the switching element of the lower arm of the switching portion is generated while the switching element of its upper arm is in an OFF state, when the direct output voltage is higher than the input alternating voltage, and a voltage at an ac input terminal between the rectifying elements of the switching portion is lower than a voltage at an ac input terminal between the rectifying elements of the rectifying portion.
摘要翻译：提供了适于输出高于交流输入电压的全波整流电压的直流电压的交流/直流转换电路，其包括交流电流滤波器，以及具有耦合到直流的正极和负极的电容器全波整流电路的输出侧。全波整流电路包括具有上臂和下臂的开关部分，每个臂具有半导体整流元件和自换向半导体开关元件，以及具有上臂和下臂的整流部分，每个具有半导体整流元件。全波整流电路的上臂中的半导体整流元件具有与正电极耦合的公共阴极，并且下臂中的半导体整流元件具有与负电极耦合的公共阳极。交流/直流转换电路还包括设置在全波整流电路的上臂的整流元件的耦合点和负极之间的电阻器。在操作中，当上臂的开关元件处于关闭状态时，当直接输出电压高于输入时，产生用于控制开关部分的下臂的开关元件的ON / OFF状态的信号交流电压，并且交换部分的整流元件之间的交流输入端子处的电压低于整流部分的整流元件之间的交流输入端子处的电压。

10. 发明授权

US5906262A Positioning control system for a non-contacting magnetic conveyor system 失效
标题翻译：非接触式磁力输送机系统的定位控制系统
公开(公告)号：US5906262A
公开(公告)日：1999-05-25
申请号：US7790
申请日：1998-01-15
申请人： Hiroshi Miki
发明人： Hiroshi Miki
IPC分类号： F16H19/04 , B65G54/02 , F16H25/24 , B65G35/00
CPC分类号： B65G54/02
摘要： A positioning control system is used to control the stoppage of a conveyed article stably and with good repeatability with a magnetic conveyor system element on the receiving side when a conveyed article is passed between magnetic conveyor device elements in a noncontacting magnetic conveyor system configured from at least two magnetic conveyor system elements. The system comprises two independently operating magnetic conveyor system elements, and is provided with drive shafts 18A-18C, each of which has helical magnetic poles at its surface, and a guide path 14 along which a carrier 13 travels, and the carrier is equipped with magnetic poles of equal pitch to the pitch of the helical magnetic poles. When the rotary shafts rotate, the carrier moves over the guide path by a magnetic coupling action and is passed between the magnetic conveyor system elements. The system further includes a rotation angle sensor 34 which senses a specific rotation angle of the drive shaft, a position check sensor 35 which senses the reception of the carrier, and control units 32A and 32B which position the carrier when the sensing of both sensors 34, 35 has been performed synchronously.
摘要翻译：使用定位控制系统，当输送物品在非接触式磁性输送机系统中的磁性输送装置元件之间通过时，可以稳定地控制所输送的物品的停止并且在接收侧具有良好的可重复性，两个磁性输送系统元件。该系统包括两个独立操作的磁性输送机系统元件，并且设置有驱动轴18A-18C，每个驱动轴在其表面具有螺旋磁极，以及引导路径14，载体13沿着导轨14行进，并且载体配备有螺距相当于螺旋磁极间距的磁极。当旋转轴旋转时，载体通过磁耦合作用在引导路径上移动并且在磁性输送系统元件之间通过。该系统还包括感测驱动轴的特定旋转角度的旋转角传感器34，感测载体的接收的位置检查传感器35以及当两个传感器34的感测时定位载体的控制单元32A和32B ，35已经同步执行。

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