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51. 发明授权

US6011714A Semiconductor circuit capable of storing a plurality of analog or multi-valued data 失效
标题翻译：能够存储多个模拟或多值数据的半导体电路
公开(公告)号：US6011714A
公开(公告)日：2000-01-04
申请号：US19270
申请日：1998-02-05
申请人： Tadashi Shibata , Tadahiro Ohmi , Yuichiro Yamashita
发明人： Tadashi Shibata , Tadahiro Ohmi , Yuichiro Yamashita
IPC分类号： G11C16/04 , G11C11/56 , G11C27/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C27/005 , G11C2211/5612
摘要： A semiconductor circuit assembly is capable of accurately storing a plurality of analog or multi-valued data using circuitry having a small surface area. The circuit assembly includes a first circuit provided in the form of a target memory cell device comprising memory cells which conduct the writing and storage of analog signals. The first circuit has output terminals for outputting stored values to the exterior as voltage signals. Mechanisms supply at least two index voltages. A second circuit performs the function of halting the writing of the analog signals when the output signal at the first circuit output terminals reaches a value representing a desired voltage plus the difference between the two index voltages.
摘要翻译：半导体电路组件能够使用具有小表面积的电路来精确地存储多个模拟或多值数据。电路组件包括以目标存储单元装置的形式提供的第一电路，其包括进行模拟信号的写入和存储的存储单元。第一电路具有用于将存储的值作为电压信号输出到外部的输出端子。机制提供至少两个指标电压。当第一电路输出端的输出信号达到表示期望电压的值加上两个指标电压之间的差时，第二电路执行停止模拟信号写入的功能。

52. 发明授权

US5982462A Inverse stagger or planar type thin-film transistor device and liquid-crystal display apparatus having floating gate electrode which is capacitively coupled with one or more input electrodes 失效
标题翻译：具有浮动栅电极的反交错或平面型薄膜晶体管器件和液晶显示装置，其具有与一个或多个输入电极电容耦合
公开(公告)号：US5982462A
公开(公告)日：1999-11-09
申请号：US812776
申请日：1997-03-06
申请人： Akira Nakano , Tadashi Shibata , Tadahiro Ohmi
发明人： Akira Nakano , Tadashi Shibata , Tadahiro Ohmi
IPC分类号： G02F1/136 , G02F1/1345 , G02F1/1362 , G02F1/1368 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/04
CPC分类号： H01L27/1214 , G02F1/1368 , G02F1/13454 , H01L29/78669
摘要： A thin film transistor device with its leakage current being controlled is provided. With such a thin film transistor device incorporated, a liquid crystal display apparatus presents a high-contrast image at a reduced power consumption. The thin film transistor is formed on an insulating substrate. The gate electrode of the transistor is electrically floating gate electrode, which is capacitance coupled to one or more input electrodes. The liquid crystal display apparatus incorporates the thin film transistor in its switching element and/or driving circuit.
摘要翻译：提供了一种其漏电流被控制的薄膜晶体管器件。通过并入这种薄膜晶体管器件，液晶显示装置以降低的功耗呈现高对比度图像。薄膜晶体管形成在绝缘基板上。晶体管的栅电极是电浮置栅电极，其电容耦合到一个或多个输入电极。液晶显示装置在其开关元件和/或驱动电路中并入薄膜晶体管。

53. 发明授权

US5923205A Semiconductor arithmetic circuit 失效
标题翻译：半导体运算电路
公开(公告)号：US5923205A
公开(公告)日：1999-07-13
申请号：US930372
申请日：1997-11-07
申请人： Tadashi Shibata , Tadahiro Ohmi , Masahiro Konda
发明人： Tadashi Shibata , Tadahiro Ohmi , Masahiro Konda
IPC分类号： G06G7/26 , G06G7/42
CPC分类号： G06G7/26
摘要： A semiconductor arithemetic circuit which performs calculation of an analog vector with a high accuracy at a high speed. A semiconductor arithemetic circuit having a plurality of MOS type transistors, wherein the source electrodes are connected to one another, the gate electrodes of the MOS type transistors are connected to a signal line having a prescribed potential via switching elements, and at least one input electrode is capacitively coupled with the gate electrodes; wherein circuitry is provided for applying first and second input voltages, respectively, to the input electrodes of at least one pair of first and second MOS type transistors among the plurality of MOS type transistors, and for equalizing potentials of the gate electrodes to the potential of the signal line by allowing the switching elements to conduct, and further circuitry means is provided for inputting the second and first input voltages into, respectively, the input electrodes of the first and second MOS type transistors after placing said gate electrodes in an electrically floating state by turning the switching elements off.
摘要翻译： PCT No.PCT / JP96 / 00882 Sec。 371日期：1997年11月7日 102（e）日期1997年11月7日PCT 1996年4月1日PCT PCT。 WO96 / 30853 PCT出版物日期：1996年10月3日一种以高速度高精度地进行模拟矢量的计算的半导体仿真电路。一种具有多个MOS型晶体管的半导体仿真电路，其中源极彼此连接，MOS型晶体管的栅电极通过开关元件连接到具有规定电位的信号线，并且至少一个输入电极与栅电极电容耦合; 其中提供电路，用于将多个MOS型晶体管中的至少一对第一和第二MOS型晶体管的输入电极分别施加第一和第二输入电压，并将栅电极的电位与信号线通过允许开关元件导通，并且还提供另外的电路装置，用于在将所述栅电极置于电浮动状态之后将第二和第一输入电压分别输入到第一和第二MOS型晶体管的输入电极中通过关闭开关元件。

54. 发明授权

US5784018A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：US5784018A
公开(公告)日：1998-07-21
申请号：US702689
申请日：1996-08-12
申请人： Tadahiro Ohmi , Takeo Yamashita , Tadashi Shibata
发明人： Tadahiro Ohmi , Takeo Yamashita , Tadashi Shibata
IPC分类号： G11C11/56 , G11C27/00 , H03M1/12
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/54 , G11C2211/5611 , G11C7/16
摘要： The invention provides a semiconductor circuit which can fetch and store analog and multilevel data by using a simple circuit. The invention also provides a multilevel memory which can freely change the number of quantizing levels by using external signals. This semiconductor circuit comprises a first circuit which converts first signals into a group of quantized signals, a second circuit which converts the signal group into second multilevel signals, and structure which feeds back the second signals to the first circuit as first signals. The semiconductor circuit further has a structure to electrically separates at least one signal included in the signal group from the input of the second circuit, and structure which feeds back the second signals to the input of the second circuit instead of the signal previously separated.
摘要翻译： PCT No.PCT / JP95 / 00204 Sec。 371日期：1996年8月12日 102（e）日期1996年8月12日PCT提交1995年2月14日PCT公布。 WO95 / 22146 PCT公开号日期：1995年8月17日本发明提供一种半导体电路，其可以通过使用简单的电路来获取和存储模拟和多电平数据。本发明还提供一种可以通过使用外部信号自由地改变量化电平数量的多电平存储器。该半导体电路包括将第一信号转换成一组量化信号的第一电路，将信号组转换成第二多电平信号的第二电路，以及将第二信号作为第一信号反馈到第一电路的结构。半导体电路还具有将包括在信号组中的至少一个信号与第二电路的输入电隔离的结构，以及将第二信号反馈到第二电路的输入而不是先前分离的信号的结构。

55. 发明授权

US5469085A Source follower using two pairs of NMOS and PMOS transistors 失效
标题翻译：源极跟随器使用两对NMOS和PMOS晶体管
公开(公告)号：US5469085A
公开(公告)日：1995-11-21
申请号：US87675
申请日：1993-10-13
申请人： Tadashi Shibata , Tadahiro Ohmi
发明人： Tadashi Shibata , Tadahiro Ohmi
IPC分类号： G06N3/063 , H01L27/115 , H01L29/788 , H03F3/50 , H03K17/00 , H03K17/16 , H03K17/687 , H03K19/0948
CPC分类号： G06N3/0635 , H01L27/115 , H01L29/7881 , H03F3/505 , H03K17/164 , H03K17/6872 , H03K2217/0036
摘要： A source follower circuit which operates at high speed and maintains low power consumption and which includes a pair of small, normally on, NMOS and PMOS transistors and a pair of large, normally off, NMOS and PMOS transistors. The two pairs of transistors are connected in parallel. In each pair of transistors the sources and the gates of the NMOS and PMOS transistors are connected to each other. Furthermore, the threshold voltages of the transistors must be set so that: large NMOS transistor voltage>small PMOS transistor voltage>small NMOS transistor voltage>large PMOS transistor voltage, or so that small PMOS transistor voltage>large NMOS transistor voltage>large PMOS transistor voltage>small NMOS transistor voltage.
摘要翻译： PCT No.PCT / JP92 / 00019 Sec。 371日期：1993年10月13日 102（e）日期1993年10月13日PCT提交1992年1月13日PCT公布。出版物WO92 / 12575 日期1992年7月23日。源极跟随器电路以高速运行并保持低功耗，并且包括一对小的，常导通的NMOS和PMOS晶体管以及一对大的常闭NMOS和PMOS晶体管。两对晶体管并联连接。在每对晶体管中，NMOS和PMOS晶体管的源极和栅极彼此连接。此外，晶体管的阈值电压必须设置为：大NMOS晶体管电压>小PMOS晶体管电压>小NMOS晶体管电压>大PMOS晶体管电压，或使PMOS晶体管电压小>大NMOS晶体管电压>大PMOS晶体管电压>小型NMOS晶体管电压。

56. 发明授权

US5316645A Plasma processing apparatus 失效
标题翻译：等离子体处理装置
公开(公告)号：US5316645A
公开(公告)日：1994-05-31
申请号：US22599
申请日：1993-02-17
申请人： Atsushi Yamagami , Nobuyuki Okamura , Tadahiro Ohmi , Haruhiro H. Goto , Tadashi Shibata
发明人： Atsushi Yamagami , Nobuyuki Okamura , Tadahiro Ohmi , Haruhiro H. Goto , Tadashi Shibata
IPC分类号： C23C14/34 , C23C14/35 , C23C16/509 , H01J37/34
CPC分类号： C23C14/3435 , C23C14/345 , C23C14/35 , C23C16/509 , H01J37/32697 , H01J37/3405 , H01J2237/332
摘要： A plasma processing apparatus comprises: a first electrode connectable with a plasma generating power source; a second electrode capable of supporting a substrate to be subjected to a plasma-involving surface treatment; a third electrode enclosing a space between the first and second electrodes, all the electrodes being positioned in an evacuatable chamber; and potential control means for controlling the potential of the third electrode.
摘要翻译：等离子体处理装置包括：可与等离子体发生电源连接的第一电极; 第二电极，其能够支撑待进行等离子体相关表面处理的基板; 封闭第一和第二电极之间的空间的第三电极，所有电极都位于可抽空的腔室中; 以及用于控制第三电极的电位的电位控制装置。

57. 发明授权

US06949478B2 Oxide film forming method 失效
标题翻译：氧化膜成型方法
公开(公告)号：US06949478B2
公开(公告)日：2005-09-27
申请号：US10120628
申请日：2002-04-11
申请人： Tadahiro Ohmi , Takashi Imaoka , Hisayuki Shimada , Nobuhiro Konishi , Mizuho Morita , Takeo Yamashita , Tadashi Shibata , Hidetoshi Wakamatsu , Jinzo Watanabe , Shintaro Aoyama , Masakazu Nakamura
发明人： Tadahiro Ohmi , Takashi Imaoka , Hisayuki Shimada , Nobuhiro Konishi , Mizuho Morita , Takeo Yamashita , Tadashi Shibata , Hidetoshi Wakamatsu , Jinzo Watanabe , Shintaro Aoyama , Masakazu Nakamura
IPC分类号： B01J19/08 , C23C8/10 , C23C8/36 , C23C14/02 , C23C14/48 , C23C16/02 , C23C16/44 , C30B23/02 , C30B25/02 , G01N23/00 , H01L21/66 , H01L21/31
CPC分类号： C30B23/02 , C23C8/10 , C23C8/36 , C23C14/022 , C23C14/48 , C23C16/02 , C23C16/4401 , C30B25/02 , C30B29/16 , Y10S438/903
摘要： A method of forming an oxide film having high insularity capability is performed within an ultra clean environment, using charged particles.
摘要翻译：使用带电粒子在超清洁环境下进行形成具有高绝缘性的氧化膜的方法。

58. 发明授权

US06606119B1 Semiconductor arithmetic circuit 失效
标题翻译：半导体运算电路
公开(公告)号：US06606119B1
公开(公告)日：2003-08-12
申请号：US09039126
申请日：1998-03-13
申请人： Tadashi Shibata , Tadahiro Ohmi
发明人： Tadashi Shibata , Tadahiro Ohmi
IPC分类号： H04N5208
CPC分类号： H04N5/357 , H04N5/142
摘要： The present invention has as an object thereof to provide a semiconductor arithmetic circuit which is capable of conducting edge accentuation processing, edge detection processing, and noise removal by means of averaging processing of an image, using extremely simple circuitry. A semiconductor arithmetic circuit is provided with an amplifier circuit in which an input terminal is connected to the gate electrode of at least one MOS type transistor, a first signal input terminal, which is connected with the input terminal via a first switching element, and a plurality of second signal input terminals, which are connected with the input terminal via a capacity element; wherein a mechanism is provided for opening the first switching element in a state in which a first signal voltage is applied to the input terminal and a predetermined second input signal voltage group is applied to the second signal input terminals, and for thereafter applying a predetermined third input signal voltage group to the second signal input terminals, and wherein the amplifier circuit comprises a source follower circuit or a voltage follower circuit.
摘要翻译：本发明的目的是提供一种半导体运算电路，其能够通过使用非常简单的电路的图像的平均处理来进行边缘突出处理，边缘检测处理和噪声去除。半导体运算电路设置有放大电路，其中输入端连接到至少一个MOS型晶体管的栅电极，经由第一开关元件与输入端连接的第一信号输入端和多个第二信号输入端，经由电容元件与输入端连接; 其特征在于，提供一种机构，用于在将第一信号电压施加到输入端子并且将预定的第二输入信号电压组施加到第二信号输入端子的状态下打开第一开关元件，然后施加预定的第三输入信号电压组到第二信号输入端，并且其中放大器电路包括源极跟随器电路或电压跟随器电路。

59. 发明授权

US5818081A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5818081A
公开(公告)日：1998-10-06
申请号：US656288
申请日：1996-07-01
申请人： Tadahiro Ohmi , Tadashi Shibata , Hideo Kosaka , Takeo Yamashita
发明人： Tadahiro Ohmi , Tadashi Shibata , Hideo Kosaka , Takeo Yamashita
IPC分类号： G06G7/60 , G06N3/063 , G11C27/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： G11C27/005 , G06N3/063 , G06N3/0635 , H01L29/42324 , H01L29/7881
摘要： Synapse can be formed from a smaller number of elements in a low-power semiconductor device, which realize a highly integrated neural network. Precise modifications of synapse weighting become possible and a neuron computer chip of a practical level can be accomplished. The semiconductor device includes a first electrode for charge injection, connected to a floating gate through a first insulating film; a second electrode for applying programming pulses, connected to the floating gate through a second insulating film, and a MOS transistor using the floating gate as its gate electrode, wherein the charge supplied from the source electrode of the MOS transistor sets the potential at the first electrode to a predetermined value determined by the potential of the floating gate, and charges are transferred between the floating gate and the first electrode through the first insulating film by applying a predetermined pulsating voltage to the second electrode.
摘要翻译： PCT No.PCT / JP94 / 02000 Sec。 371日期：1996年7月1日 102（e）日期1996年7月1日PCT 1994年11月29日PCT PCT。公开号WO95 / 15580 日期1995年6月8日可以在低功率半导体器件中由较少数量的元件形成，这实现了高度集成的神经网络。突触加权的精确修改成为可能，并且可以实现具有实用水平的神经元计算机芯片。半导体器件包括用于电荷注入的第一电极，通过第一绝缘膜连接到浮置栅极; 用于施加通过第二绝缘膜连接到浮置栅极的编程脉冲的第二电极和使用浮置栅极作为其栅电极的MOS晶体管，其中从MOS晶体管的源极提供的电荷将第一电极到由浮置栅极的电位确定的预定值，并且通过对第二电极施加预定的脉动电压，电荷通过第一绝缘膜在浮置栅极和第一电极之间传递。

60. 发明授权

US5745416A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5745416A
公开(公告)日：1998-04-28
申请号：US581740
申请日：1995-12-29
申请人： Tadashi Shibata , Tadahiro Ohmi , Yuichiro Yamashita
发明人： Tadashi Shibata , Tadahiro Ohmi , Yuichiro Yamashita
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , G11C27/00 , H01L21/8247 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/045 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/0441 , G11C16/0458 , G11C27/005 , G11C2211/5612 , G11C2211/5613
摘要： A non-volatile semiconductor memory which is capable of high speed and highly accurate analog data writing. The memory includes a first MOS type transistor having a first floating gate which is electrically isolated. A first electrode is capacitively coupled with the first floating gate. A second electrode is connected via a tunnel junction with the first floating gate. A third electrode is capacitively coupled with the second electrode. A second MOS type transistor interconnects the first and second electrodes. A means is provided for applying a predetermined potential difference between the first and third electrodes to thereby cause a tunnel current to flow in the tunnel junction and to store an electric charge in the first floating gate to thereby cause the second MOS type transistor to conduct when the electric charge has reached a predetermined value.
摘要翻译：一种能够进行高速和高精度模拟数据写入的非易失性半导体存储器。存储器包括具有电隔离的第一浮动栅极的第一MOS型晶体管。第一电极与第一浮栅电容耦合。第二电极经由与第一浮动栅极的隧道结连接。第三电极与第二电极电容耦合。第二MOS型晶体管互连第一和第二电极。提供了一种用于在第一和第三电极之间施加预定电位差从而使隧道电流在隧道结中流动并在第一浮栅中存储电荷从而使第二MOS型晶体管导通的装置，电荷已经达到预定值。

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