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51. 发明授权

US06406993B1 Method of defining small openings in dielectric layers 有权
标题翻译：定义介电层中小开口的方法
公开(公告)号：US06406993B1
公开(公告)日：2002-06-18
申请号：US09523439
申请日：2000-03-10
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L21/76831
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.
摘要翻译：本发明涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括形成电介质材料层，在介电材料层之上形成硬掩模层，并在硬掩模层中形成开口。所述方法还包括在所述硬掩模层中的所述开口中形成侧壁间隔物，所述开口限定缩小的开口，在所述还原开口下方的介电材料层中形成开口，以及在所述电介质层的所述开口中形成导电互连。

52. 发明授权

US06329277B1 Method of forming cobalt silicide 有权
标题翻译：形成硅化钴的方法
公开(公告)号：US06329277B1
公开(公告)日：2001-12-11
申请号：US09417839
申请日：1999-10-14
申请人： Bill Yowjuang Liu , Paul R. Besser
发明人： Bill Yowjuang Liu , Paul R. Besser
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518
摘要： A semiconductor arrangement and method of forming silicide regions includes conformally depositing a reducing material layer on a silicon substrate. A refractory metal layer is then conformally deposited on the reducing material layer. Annealing is then performed to form a refractory metal silicide layer on the silicon substrate. The metal silicide layer is a cobalt silicide and the reducing material layer includes at least one of tantalum, magnesium, aluminum or calcium. The reducing material reduces native oxide on a silicon substrate to allow the cobalt silicide to form.
摘要翻译：形成硅化物区域的半导体布置和方法包括在硅衬底上共形沉积还原材料层。然后将难熔金属层共形沉积在还原材料层上。然后进行退火以在硅衬底上形成难熔金属硅化物层。金属硅化物层是硅化钴，还原材料层包括钽，镁，铝或钙中的至少一种。还原材料减少硅衬底上的自然氧化物以形成硅化钴。

53. 发明授权

US06297107B1 High dielectric constant materials as gate dielectrics 有权
标题翻译：高介电常数材料作为栅极电介质
公开(公告)号：US06297107B1
公开(公告)日：2001-10-02
申请号：US09691228
申请日：2000-10-19
申请人： Eric Paton , Matthew S. Byunoski , Paul R. Besser , Paul L. King , Qi Xiang
发明人： Eric Paton , Matthew S. Byunoski , Paul R. Besser , Paul L. King , Qi Xiang
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/31691 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure having a gate dielectric between a gate electrode and a semiconductor substrate is formed with a high dielectric metal oxide layer by replacing a sacrificial gate oxide. Embodiments include forming the metal oxide layer by applying a chemical solution deposition of a metalorganic on to an exposed surface of the substrate followed by pyrolizing the metalorganic residue to a metal oxide.
摘要翻译：通过替代牺牲栅极氧化物，在栅电极和半导体衬底之间具有栅极电介质的半导体结构形成有高介电金属氧化物层。实施例包括通过将金属有机物的化学溶液沉积施加到基板的暴露表面上，然后将金属有机残渣热解成金属氧化物来形成金属氧化物层。

54. 发明授权

US06239494B1 Wire bonding CU interconnects 有权
标题翻译：线接CU互连
公开(公告)号：US06239494B1
公开(公告)日：2001-05-29
申请号：US09295357
申请日：1999-04-21
申请人： Paul R. Besser , Robin W. Cheung
发明人： Paul R. Besser , Robin W. Cheung
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L23/53233 , H01L23/53238 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48724 , H01L2224/85375 , H01L2924/01005 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： Wire bonding to a Cu interconnect via and Al pad with reduced Al and Cu inter-diffusion is achieved by interposing a barrier layer between the Cu interconnect and Al pad. Embodiments include forming a barrier layer of Ti, Ta, W, alloy thereof or nitride thereof, between the Cu interconnect and the Al pad.
摘要翻译：通过在Cu互连和Al焊盘之间插入势垒层，实现了通过Al和Cu互扩散而减少的Cu互连通孔和Al焊盘的引线接合。实施例包括在Cu互连和Al衬垫之间形成Ti，Ta，W的阻挡层，其合金或其氮化物。

55. 发明授权

US06204177B1 Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal 有权
$Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal$
标题翻译：通过合金化难熔金属在半导体晶片中形成结无漏电金属硅化物的方法
公开(公告)号：US06204177B1
公开(公告)日：2001-03-20
申请号：US09185515
申请日：1998-11-04
申请人： Paul R. Besser , Nick Kepler , Karsten Wieczorek
发明人： Paul R. Besser , Nick Kepler , Karsten Wieczorek
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/456 , H01L29/4933
摘要： A method of forming metal silicide in a semiconductor wafer with reduced junction leakage introduces an alloy at cobalt grain boundaries within a cobalt layer that overlays a silicon layer. The alloy element can be precipitated during deposition of the cobalt and the alloy element, or by an intermediate anneal after deposition. The cobalt layer and the silicon layer are then annealed to form metal silicide regions. By precipitating an alloy at the cobalt grain boundaries, cobalt diffusion at the grain boundaries is retarded during a first rapid thermal annealing step. Bulk diffusion is encouraged, and a more uniform silicide film with reduced interface roughness is produced. Since the interface roughness is reduced with the methods of the present invention, junction leakage is reduced. This allows shallower junctions to be fabricated, leading to devices with improved performance.
摘要翻译：在具有减少的结漏电的半导体晶片中形成金属硅化物的方法在覆盖硅层的钴层内的钴晶界处引入合金。在钴和合金元素的沉积期间，或者通过沉积后的中间退火，合金元素可以沉淀。然后将钴层和硅层退火以形成金属硅化物区域。通过在钴晶界析出合金，在第一快速热退火步骤期间，在晶界处的钴扩散被延迟。鼓励扩散，并产生具有降低的界面粗糙度的更均匀的硅化物膜。由于通过本发明的方法减小了界面粗糙度，所以结漏电减少。这允许制造较浅的结，导致具有改进性能的器件。

56. 发明授权

US06171919B2 MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation 有权
标题翻译： MOS晶体管形成工艺包括用于改善硅化物形成的后间隔蚀刻表面处理
公开(公告)号：US06171919B2
公开(公告)日：2001-01-09
申请号：US09361155
申请日：1999-07-27
申请人： Paul R. Besser , Minh Van Ngo , Simon S. Chan , Angela T. Hui
发明人： Paul R. Besser , Minh Van Ngo , Simon S. Chan , Angela T. Hui
IPC分类号： H01L21336
CPC分类号： H01L29/665
摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.
摘要翻译：通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣。实施例包括通过进行氢离子等离子体处理来除去碳质残渣。

57. 发明授权

US6165903A Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation 有权
标题翻译：在具有沉积硅层的半导体晶片中形成超浅结的方法，以减少在水化过程中的硅消耗
公开(公告)号：US6165903A
公开(公告)日：2000-12-26
申请号：US185516
申请日：1998-11-04
申请人： Paul R. Besser , Nick Kepler , Karsten Wieczorek
发明人： Paul R. Besser , Nick Kepler , Karsten Wieczorek
IPC分类号： H01L21/285 , H01L21/44
CPC分类号： H01L21/28525 , H01L21/28518
摘要： A method for forming ultra shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high resistivity metal silicide regions are formed on the gate and source/drain junctions. Silicon is then deposited in a layer on the high resistivity metal silicide regions. An annealing step is then performed to form low resistivity metal silicide regions on the gate and source/drain junctions. The deposited silicon is a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide (such as CoSi) to a low resistivity metal silicide (such as CoSi.sub.2). Since the additional silicon provided in the deposited layer is consumed, there is reduced consumption of the silicon from the ultra-shallow junctions, thereby preventing the bottom of the silicide regions from reaching the bottom of the source/drain junctions.
摘要翻译：用于在半衰期期间形成超浅结的方法，其中在硅化过程中硅消耗减少，在硫化过程中提供额外的硅。在半导体器件中形成栅极和源极/漏极结之后，在栅极和源极/漏极结上形成高电阻金属硅化物区域。然后将硅沉积在高电阻率金属硅化物区域上的层中。然后执行退火步骤以在栅极和源极/漏极结上形成低电阻率金属硅化物区域。沉积的硅是在将高电阻率金属硅化物（例如CoSi）转变成低电阻率金属硅化物（例如CoSi 2）期间用作扩散物质的硅源。由于在沉积层中提供的附加硅被消耗，所以硅从超浅结的消耗减少，从而防止硅化物区的底部到达源极/漏极结的底部。

58. 发明申请

US20140024212A1 MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE 有权
标题翻译：用于互连结构的多层障碍层
公开(公告)号：US20140024212A1
公开(公告)日：2014-01-23
申请号：US13554020
申请日：2012-07-20
申请人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
发明人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
IPC分类号： H01L21/768
CPC分类号： H01L21/76873 , H01L21/76846 , H01L21/76858 , H01L21/76883 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.
摘要翻译：形成互连结构的方法包括在基板的电介质层中形成凹部。形成粘合阻挡层以使凹部成线。第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。在粘合阻挡层上方形成有应力降低阻挡层。所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。该凹部填充有填充层。

59. 发明申请

US20100193876A1 METHOD TO REDUCE MOL DAMAGE ON NiSi 有权
标题翻译：减少镍硅膜损伤的方法
公开(公告)号：US20100193876A1
公开(公告)日：2010-08-05
申请号：US12366378
申请日：2009-02-05
申请人： Karthik Ramani , Paul R. Besser
发明人： Karthik Ramani , Paul R. Besser
IPC分类号： H01L29/49 , H01L29/78 , H01L21/77 , H01L21/18
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823814 , H01L21/823835 , H01L29/458 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.
摘要翻译：晶体管器件形成有硅化镍层，配制成防止去除上覆应力衬垫时的退化。实施方案包括具有镍化硅层的晶体管，其铂组分梯度朝向其上表面增加铂含量，即铂在远离栅电极和源/漏区的方向上增加。实施例包括形成具有第一量的铂的第一镍层，并在第一层镍上形成具有第二量铂的第二层镍，第二重量百分比的铂大于第一重量百分数。然后将镍层退火以形成铂化合物梯度朝向上表面逐渐增加的铂硅化镍层。铂浓度梯度在后续处理期间保护硅化镍层，如在蚀刻期间去除上覆的应力衬垫，从而避免器件性能的降低。

60. 发明授权

US07456062B1 Method of forming a semiconductor device 有权
公开(公告)号：US07456062B1
公开(公告)日：2008-11-25
申请号：US11209871
申请日：2005-08-23
申请人： William G. En , Thorsten Kammler , Eric N. Paton , Paul R. Besser , Simon Siu-Sing Chan
发明人： William G. En , Thorsten Kammler , Eric N. Paton , Paul R. Besser , Simon Siu-Sing Chan
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7834 , H01L21/28035 , H01L21/28123 , H01L29/42376 , H01L29/6656 , H01L29/6659 , H01L29/66628
摘要： A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.

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