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1. 发明授权

US08728931B2 Multi-layer barrier layer for interconnect structure 有权
标题翻译：用于互连结构的多层阻挡层
公开(公告)号：US08728931B2
公开(公告)日：2014-05-20
申请号：US13553977
申请日：2012-07-20
申请人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
发明人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
IPC分类号： H01L21/4763
CPC分类号： H01L23/49866 , H01L21/76846 , H01L21/76858 , H01L21/76873 , H01L21/76886 , H01L23/49827 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.
摘要翻译：形成互连结构的方法包括在基板的电介质层中形成凹部。形成粘合阻挡层以使凹部成线。第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。在粘合阻挡层上方形成有应力降低阻挡层。所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。该凹部填充有填充层。

2. 发明申请

US20140024212A1 MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE 有权
标题翻译：用于互连结构的多层障碍层
公开(公告)号：US20140024212A1
公开(公告)日：2014-01-23
申请号：US13554020
申请日：2012-07-20
申请人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
发明人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
IPC分类号： H01L21/768
CPC分类号： H01L21/76873 , H01L21/76846 , H01L21/76858 , H01L21/76883 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.
摘要翻译：形成互连结构的方法包括在基板的电介质层中形成凹部。形成粘合阻挡层以使凹部成线。第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。在粘合阻挡层上方形成有应力降低阻挡层。所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。该凹部填充有填充层。

3. 发明授权

US09269615B2 Multi-layer barrier layer for interconnect structure 有权
标题翻译：用于互连结构的多层阻挡层
公开(公告)号：US09269615B2
公开(公告)日：2016-02-23
申请号：US13554020
申请日：2012-07-20
申请人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
发明人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76873 , H01L21/76846 , H01L21/76858 , H01L21/76883 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.
摘要翻译：形成互连结构的方法包括在基板的电介质层中形成凹部。形成粘合阻挡层以使凹部成线。第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。在粘合阻挡层上方形成有应力降低阻挡层。所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。该凹部填充有填充层。

4. 发明申请

US20140021613A1 MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE 有权
公开(公告)号：US20140021613A1
公开(公告)日：2014-01-23
申请号：US13553977
申请日：2012-07-20
申请人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
发明人： Vivian W. Ryan , Xunyuan Zhang , Paul R. Besser
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/49866 , H01L21/76846 , H01L21/76858 , H01L21/76873 , H01L21/76886 , H01L23/49827 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

5. 发明申请

US20130049199A1 SILICIDATION OF DEVICE CONTACTS USING PRE-AMORPHIZATION IMPLANT OF SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：使用半导体基板的预加工植入物进行器件接触的硅化
公开(公告)号：US20130049199A1
公开(公告)日：2013-02-28
申请号：US13222469
申请日：2011-08-31
申请人： Paul R. Besser , Roy A. Carruthers , Christopher P. D'Emic , Christian Lavoie , Conal E. Murray , Kazuya Ohuchi , Christopher Scerbo , Bin Yang
发明人： Paul R. Besser , Roy A. Carruthers , Christopher P. D'Emic , Christian Lavoie , Conal E. Murray , Kazuya Ohuchi , Christopher Scerbo , Bin Yang
IPC分类号： H01L23/532 , H01L21/336 , H01L21/768
CPC分类号： H01L21/26506 , H01L21/28518 , H01L29/00 , H01L29/665 , H01L29/7833
摘要： Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to form an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A suicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.
摘要翻译：具有改进的稀土硅化物形态的硅化技术用于制造半导体器件触点。例如，用于形成硅化物的方法包括用非晶化物质注入硅层以在硅层中形成非晶硅区域，并在与非晶硅区域接触的硅层上沉积稀土金属膜。然后进行自杀处理以组合稀土金属膜和非晶硅区域，以在硅层上形成硅化物膜。

6. 发明授权

US07994038B2 Method to reduce MOL damage on NiSi 有权
标题翻译：减少NiSi上MOL损伤的方法
公开(公告)号：US07994038B2
公开(公告)日：2011-08-09
申请号：US12366378
申请日：2009-02-05
申请人： Karthik Ramani , Paul R. Besser
发明人： Karthik Ramani , Paul R. Besser
IPC分类号： H01L21/3205
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823814 , H01L21/823835 , H01L29/458 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.
摘要翻译：晶体管器件形成有硅化镍层，配制成防止去除上覆应力衬垫时的退化。实施方案包括具有镍化硅层的晶体管，其铂组分梯度朝向其上表面增加铂含量，即铂在远离栅电极和源/漏区的方向上增加。实施例包括形成具有第一量的铂的第一镍层，并在第一层镍上形成具有第二量铂的第二层镍，第二重量百分比的铂大于第一重量百分数。然后将镍层退火以形成铂化合物梯度朝向上表面逐渐增加的铂硅化镍层。铂浓度梯度在后续处理期间保护硅化镍层，如在蚀刻期间去除上覆的应力衬垫，从而避免器件性能的降低。

7. 发明授权

US07910996B2 Semiconductor device and method of manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07910996B2
公开(公告)日：2011-03-22
申请号：US12496133
申请日：2009-07-01
申请人： Paul R. Besser , Scott D. Luning
发明人： Paul R. Besser , Scott D. Luning
IPC分类号： H01L29/12
CPC分类号： H01L29/66628 , H01L29/66772
摘要： A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.
摘要翻译：公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。隔离材料凹陷在半导体层的主表面下方的沟槽区域内。形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

8. 发明申请

US20080182407A1 METHOD OF FORMING VIAS IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件中形成VIAS的方法
公开(公告)号：US20080182407A1
公开(公告)日：2008-07-31
申请号：US11669700
申请日：2007-01-31
申请人： Jun Zhai , Christy Woo , Kok-Yong Yiang , Paul R. Besser , Richard C. Blish , Christine Hau-Reige
发明人： Jun Zhai , Christy Woo , Kok-Yong Yiang , Paul R. Besser , Richard C. Blish , Christine Hau-Reige
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76852 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A via is formed in contact with a conductive line, whereby the via is offset from the conductive line so that the via extends beyond the conductive line. In accordance with a specific embodiment, a portion of the via contacts a sidewall of the conductive line.
摘要翻译：通孔形成为与导电线接触，由此通孔偏离导线，使得通孔延伸超过导线。根据具体实施例，通孔的一部分接触导线的侧壁。

9. 发明申请

US20080150011A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 审中-公开
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080150011A1
公开(公告)日：2008-06-26
申请号：US11958646
申请日：2007-12-18
申请人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
发明人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.
摘要翻译：提供一种用于形成集成电路系统的方法，包括形成具有芯区域和周边区域的衬底，在芯区域中的衬底上形成电荷存储堆叠，形成具有堆叠集管的栅极堆叠，堆叠集束具有金属部分衬底，并且在电荷存储堆叠上形成具有堆叠头的存储器系统。

10. 发明授权

US07217660B1 Method for manufacturing a semiconductor component that inhibits formation of wormholes 有权
标题翻译：制造抑制虫洞形成的半导体部件的方法
公开(公告)号：US07217660B1
公开(公告)日：2007-05-15
申请号：US11109964
申请日：2005-04-19
申请人： Connie Pin-Chin Wang , Paul R. Besser , Jinsong Yin , Hieu T. Pham , Minh Van Ngo
发明人： Connie Pin-Chin Wang , Paul R. Besser , Jinsong Yin , Hieu T. Pham , Minh Van Ngo
IPC分类号： H01L21/22
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/28556 , H01L21/28562 , H01L21/76843 , H01L21/76846 , H01L29/6659
摘要： A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.
摘要翻译：一种制造半导体元件的方法，该半导体元件抑制在半导体衬底中形成虫洞。在设置在半导体衬底上的电介质层中形成接触开口。接触开口露出半导体衬底的一部分。在半导体衬底的暴露部分上并沿着接触开口的侧壁形成氧化物牺牲层。硅烷与六氟化钨反应形成氢氟酸蒸汽和钨。氢氟酸蒸气蚀刻掉牺牲氧化物层，并且在半导体衬底的暴露部分上形成薄的钨层。在形成钨的薄层之后，可以改变反应物以更快地用钨填充接触开口。

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