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51. 发明申请

US20110215321A1 POLYSILICON RESISTOR AND E-FUSE FOR INTEGRATION WITH METAL GATE AND HIGH-K DIELECTRIC 有权
标题翻译：用于与金属栅和高K电介质集成的多晶硅电阻器和电子熔断器
公开(公告)号：US20110215321A1
公开(公告)日：2011-09-08
申请号：US12719289
申请日：2010-03-08
申请人： Roger A. Booth, JR. , Kangguo Cheng , Rainer Loesing , Chengwen Pei , Xiaojun Yu
发明人： Roger A. Booth, JR. , Kangguo Cheng , Rainer Loesing , Chengwen Pei , Xiaojun Yu
IPC分类号： H01L29/12 , H01L21/02 , H01L21/768 , H01L29/86 , H01L23/525
CPC分类号： H01L21/02 , H01L21/768 , H01L23/525 , H01L29/12 , H01L29/86 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate.
摘要翻译：提供了一种用于制造电阻性多晶半导体器件的方法，例如诸如半导体集成电路的微电子元件的多晶硅电阻器。该方法可以包括：（a）形成层叠堆叠，其包括与衬底的单晶半导体区域的表面接触的电介质层，覆盖在电介质层上的金属栅极层，与金属栅极层相邻的第一多晶半导体区域，掺杂剂类型的n或p，以及第二多晶半导体区域，其与所述第一多晶半导体区域与所述金属栅极层隔开并邻接所述第一多晶半导体区域; 和（b）形成与所述第二多晶半导体区域导电连通的第一和第二触点，所述第一和第二触点间隔开以达到期望的电阻。在其变型中，形成电熔丝，其包括连续的硅化物区域，电流可以通过该硅化物区域通过以熔断熔丝。在同一衬底上制造金属栅极场效应晶体管（FET）的同时可以同时采用制造多晶硅电阻器或电熔丝的步骤。

52. 发明申请

US20090242953A1 SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE 有权
标题翻译：与高K /金属闸门兼容的低压电容器
公开(公告)号：US20090242953A1
公开(公告)日：2009-10-01
申请号：US12059174
申请日：2008-03-31
申请人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L27/108 , H01L21/8242 , G06F17/50
CPC分类号： H01L27/0629
摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
摘要翻译：通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。第二极性可以与第一极性相反。额外的植入物可以减少第二细胞中的ESR。

53. 发明授权

US08298908B2 Structure and method for forming isolation and buried plate for trench capacitor 有权
标题翻译：用于形成沟槽电容器的隔离和掩埋板的结构和方法
公开(公告)号：US08298908B2
公开(公告)日：2012-10-30
申请号：US12704084
申请日：2010-02-11
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

54. 发明申请

US20110193193A1 STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR 有权
标题翻译：用于形成用于TRENCH电容器的隔离和平板的结构和方法
公开(公告)号：US20110193193A1
公开(公告)日：2011-08-11
申请号：US12704084
申请日：2010-02-11
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

55. 发明授权

US08420476B2 Integrated circuit with finFETs and MIM fin capacitor 有权
标题翻译：集成电路与finFET和MIM鳍电容器
公开(公告)号：US08420476B2
公开(公告)日：2013-04-16
申请号：US12789013
申请日：2010-05-27
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Toshiharu Furukawa , Chengwen Pei
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Toshiharu Furukawa , Chengwen Pei
IPC分类号： H01L21/8238
CPC分类号： H01L27/0629 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/845 , H01L27/1211 , H01L28/91
摘要： An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; and forming a fin capacitor comprising the first conductor, the second dielectric, and the second conductor.
摘要翻译：公开了一种具有finFET和金属 - 绝缘体 - 金属（MIM）鳍片电容器及其制造方法的集成电路。一种方法包括形成包括第一电介质和第一导体的第一finFET; 形成包括第二电介质和第二导体的第二finFET; 以及形成包括所述第一导体，所述第二电介质和所述第二导体的散热片电容器。

56. 发明授权

US07759766B2 Electrical fuse having a thin fuselink 失效
标题翻译：电熔丝具有薄的熔丝
公开(公告)号：US07759766B2
公开(公告)日：2010-07-20
申请号：US11843047
申请日：2007-08-22
申请人： Roger A. Booth, Jr. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, Jr. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.
摘要翻译：薄半导体层在半导体衬底上形成并图案化以在浅沟槽隔离上以及在阳极半导体区域和阴极半导体区域之间形成薄的半导体熔丝。在金属化期间，由于半导体软管中的所有半导体材料与金属反应而形成金属半导体合金，所以将半导体熔融金属转换为薄金属半导体合金熔丝。本发明的电熔丝包括薄金属半导体合金熔丝，金属半导体合金阳极和金属半导体合金阴极。与现有技术的电熔丝相比，薄金属半导体合金熔体具有较小的横截面积。与现有技术的电熔丝相比，可以获得与现有技术的电熔丝相当的在熔丝中的电流密度和在熔丝与阴极或阳极之间的界面处的电流发散度，而不是现有技术的电熔丝。

57. 发明授权

US08629009B2 Programmable high-k/metal gate memory device 有权
标题翻译：可编程高k /金属栅极存储器件
公开(公告)号：US08629009B2
公开(公告)日：2014-01-14
申请号：US13433423
申请日：2012-03-29
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/28282 , H01L21/823462 , H01L21/823468 , H01L27/1052 , H01L27/11573 , H01L29/4234 , H01L29/4983 , H01L29/517 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.
摘要翻译：提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和半导体衬底上的第二金属栅电极。在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质到第二金属栅电极的侧壁。

58. 发明申请

US20100181620A1 STRUCTURE AND METHOD FOR FORMING PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE 有权
标题翻译：用于形成可编程高K /金属栅存储器件的结构和方法
公开(公告)号：US20100181620A1
公开(公告)日：2010-07-22
申请号：US12355954
申请日：2009-01-19
申请人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
发明人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
IPC分类号： H01L29/786 , H01L21/336 , H01L21/331 , H01L21/8234 , H01L27/115 , H01L21/8232 , H01L29/78
CPC分类号： H01L29/78 , H01L21/28282 , H01L21/823462 , H01L21/823468 , H01L27/1052 , H01L27/11573 , H01L29/4234 , H01L29/4983 , H01L29/517 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack overlying a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode overlying a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.
摘要翻译：提供了一种制造存储器件的方法，其可以开始形成覆盖在半导体衬底上的层叠栅极堆叠并且图案化停止在层状栅极堆叠的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和半导体衬底上的第二金属栅电极。在下一个处理顺序中，在第一金属栅电极上形成至少一个间隔物，该第一金属栅电极覆盖高k栅极电介质层的一部分，其中暴露高k栅极电介质的剩余部分。蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质到第二金属栅电极的侧壁。

59. 发明申请

US20090101956A1 EMBEDDED TRENCH CAPACITOR HAVING A HIGH-K NODE DIELECTRIC AND A METALLIC INNER ELECTRODE 有权
标题翻译：具有高K节点电介质和金属内电极的嵌入式电容器
公开(公告)号：US20090101956A1
公开(公告)日：2009-04-23
申请号：US11873728
申请日：2007-10-17
申请人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L27/108 , H01G4/00 , H01L21/8242
CPC分类号： H01L27/1087
摘要： A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region.
摘要翻译：在半导体衬底和衬垫层中形成深沟槽，并填充有虚拟节点电介质和虚设沟槽填充物。在半导体衬底中形成浅沟槽隔离结构。去除焊盘层之后，在器件区域中形成虚拟栅极结构。在虚拟栅极结构上形成第一电介质层，并且填充虚拟沟槽的突出部分，然后进行平坦化。虚拟结构被去除。深沟槽和通过去除伪栅极结构形成的空腔填充有高介电常数材料层和金属层，其形成深沟槽中的高k节点电介质和深沟槽电容器的金属内电极以及在器件区域中的高k栅极电介质和金属栅极。

60. 发明申请

US20090051002A1 ELECTRICAL FUSE HAVING A THIN FUSELINK 失效
标题翻译：电子保险丝
公开(公告)号：US20090051002A1
公开(公告)日：2009-02-26
申请号：US11843047
申请日：2007-08-22
申请人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.
摘要翻译：薄半导体层在半导体衬底上形成并图案化以在浅沟槽隔离上以及在阳极半导体区域和阴极半导体区域之间形成薄的半导体熔丝。在金属化期间，由于半导体软管中的所有半导体材料与金属反应而形成金属半导体合金，所以将半导体熔融金属转换为薄金属半导体合金熔丝。本发明的电熔丝包括薄金属半导体合金熔丝，金属半导体合金阳极和金属半导体合金阴极。与现有技术的电熔丝相比，薄金属半导体合金熔体具有较小的横截面积。与现有技术的电熔丝相比，可以获得与现有技术的电熔丝相当的在熔丝中的电流密度和在熔丝与阴极或阳极之间的界面处的电流发散度，而不是现有技术的电熔丝。

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