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51. 发明申请

US20070099405A1 Methods for fabricating multi-terminal phase change devices 有权
标题翻译：制造多端相变装置的方法
公开(公告)号：US20070099405A1
公开(公告)日：2007-05-03
申请号：US11267789
申请日：2005-11-03
申请人： Antonietta Oliva , Louis Kordus , Narbeh Derhacobian , Vei-Han Chan , Thomas Stewart
发明人： Antonietta Oliva , Louis Kordus , Narbeh Derhacobian , Vei-Han Chan , Thomas Stewart
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/126
摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.
摘要翻译：相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其导电性可以根据施加到控制电极的控制信号进行修改。这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。加热元件的电阻不影响相变装置的总电阻。编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

52. 发明申请

US20070097740A1 Content-addressable memory having phase change material devices 有权
标题翻译：具有相变材料装置的内容寻址存储器
公开(公告)号：US20070097740A1
公开(公告)日：2007-05-03
申请号：US11267781
申请日：2005-11-03
申请人： Narbeh Derhacobian , Colin Murphy
发明人： Narbeh Derhacobian , Colin Murphy
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C15/046
摘要： Content-addressable memory (CAM) cells comprised of phase change material devices (PCMDs), including PCMD-based binary CAM cells (PCMD-based BCAM cells), PCMD-based ternary CAM cells (PCMD-based TCAM cells), and PCMD-based universal CAM cells (PCMD-based UCAM cells). The PCMDs of the various PCMD-based CAM cells are configured and programmed in a manner that allows a logic “0” or a logic “1” to be stored by the CAM cell. The logic value stored by a given PCMD-based CAM cell depends on the program states of the PCMDs. A program state of a PCMD is determined by whether the phase change material of the PCMD has been allowed to solidify to a crystalline, low-resistance state during a programming operation, or whether the phase change material of the PCMD is forced to solidify to an amorphous, high-resistance state during the programming operation.
摘要翻译：由包括基于PCMD的二进制CAM单元（基于PCMD的BCAM单元），基于PCMD的三元CAM单元（基于PCMD的TCAM单元）和PCMD-based三元CAM单元组成的包括相变材料装置（PCMD）的内容寻址存储器（CAM）基于通用的CAM单元（基于PCMD的UCAM单元）。各种基于PCMD的CAM单元的PCMD以允许CAM单元存储逻辑“0”或逻辑“1”的方式进行配置和编程。由给定基于PCMD的CAM单元存储的逻辑值取决于PCMD的程序状态。 PCMD的编程状态由PCMD的相变材料是否已被允许在编程操作期间凝固成晶体，低电阻状态，或PCMD的相变材料是否被迫固化为非线性，高电阻状态。

53. 发明授权

US06618290B1 Method of programming a non-volatile memory cell using a baking process 失效
标题翻译：使用烘烤过程对非易失性存储单元进行编程的方法
公开(公告)号：US06618290B1
公开(公告)日：2003-09-09
申请号：US09880366
申请日：2001-06-13
申请人： Janet S. Y. Wang , Narbeh Derhacobian
发明人： Janet S. Y. Wang , Narbeh Derhacobian
IPC分类号： G11C1604
CPC分类号： G11C16/0475
摘要： A method of programming that includes programming a fresh memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. Baking the programmed fresh cell causing a charge loss in the channel while the remaining charge within the channel is distributed more locally at the first region when compared to the distribution of charge prior to the baking.
摘要翻译：一种编程方法，包括用包括第一区域和第二区域以及沟道上方的栅极的衬底编程新鲜存储器单元以及包含第一电荷量的电荷捕获区域。烘烤编程的新鲜细胞，导致通道中的电荷损失，而与烘焙前的电荷分布相比，通道内的剩余电荷在第一区域更局部分布。

54. 发明授权

US06519182B1 Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure 有权
标题翻译：使用热载流子注入来控制具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元中的过度编程
公开(公告)号：US06519182B1
公开(公告)日：2003-02-11
申请号：US09902332
申请日：2001-07-10
申请人： Narbeh Derhacobian , Daniel Sobek
发明人： Narbeh Derhacobian , Daniel Sobek
IPC分类号： G11C1604
CPC分类号： G11C16/3486 , G11C16/0475 , G11C16/10 , G11C16/3468
摘要： A programming operation using hot carrier injection is performed on a non volatile memory cell having an oxide-nitride-oxide structure by applying a first train of voltage pulses to he drain and a second train of voltage pulses to the gate. The programming method of the present invention prevents over-programming, minimizes programming time, and increases memory cell endurance and reliability.
摘要翻译：对具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元进行使用热载流子注入的编程操作，通过向栅极施加第一列电压脉冲，将第二列电压脉冲施加到栅极。本发明的编程方法防止过度编程，使编程时间最小化，并增加存储单元的耐久性和可靠性。

55. 发明授权

US06465303B1 Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory 有权
标题翻译：制造用于氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性存储器的间隔物蚀刻掩模的方法
公开(公告)号：US06465303B1
公开(公告)日：2002-10-15
申请号：US09885490
申请日：2001-06-20
申请人： Mark T. Ramsbey , Narbeh Derhacobian , Janet Wang , Angela Hui , Tuan Pham , Ravi Sunkavalli , Mark Randolph
发明人： Mark T. Ramsbey , Narbeh Derhacobian , Janet Wang , Angela Hui , Tuan Pham , Ravi Sunkavalli , Mark Randolph
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.
摘要翻译：本发明的一个方面涉及一种在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体存储器件中形成间隔物的方法，包括以下步骤：提供具有核心区域和外围区域的半导体衬底，包含SONOS型存储单元的核心区域和包含栅极晶体管的外围区域; 将第一注入植入到所述芯区域中，并将第一注入植入所述半导体衬底的周边区域; 在所述半导体衬底上形成隔离材料; 掩蔽所述芯区域并在所述周边区域中形成与所述栅极晶体管相邻的间隔物; 以及将第二植入物植入所述半导体衬底的周边区域。

56. 发明授权

US06456536B1 Method of programming a non-volatile memory cell using a substrate bias 有权
标题翻译：使用衬底偏置来编程非易失性存储单元的方法
公开(公告)号：US06456536B1
公开(公告)日：2002-09-24
申请号：US09884409
申请日：2001-06-19
申请人： Daniel Sobek , Timothy J. Thurgate , Janet Wang , Narbeh Derhacobian
发明人： Daniel Sobek , Timothy J. Thurgate , Janet Wang , Narbeh Derhacobian
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/12
摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region and applying a third voltage that is constant and negative to the substrate so that the effect of spillover electrons is substantially reduced when compared with when the third constant voltage is absent.
摘要翻译：一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。该方法包括在栅极上施加恒定的第一电压，在第一区域上施加第二恒定电压，并向衬底施加恒定和负的第三电压，使得当与第三区域相比时，溢出电子的效应显着降低不存在恒定电压。

57. 发明授权

US06456533B1 Higher program VT and faster programming rates based on improved erase methods 有权
标题翻译：基于改进的擦除方法，更高的程序VT和更快的编程速率
公开(公告)号：US06456533B1
公开(公告)日：2002-09-24
申请号：US09796282
申请日：2001-02-28
申请人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S.Y. Wang , Kulachet K.T. Tanpairoj
发明人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S.Y. Wang , Kulachet K.T. Tanpairoj
IPC分类号： G11C1134
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/50 , G11C29/50004
摘要： A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.
摘要翻译：用于编程双位存储器单元的存储器阵列的正常位的方法和系统通过以基本上高的delta VT编程来实现。基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在更高的温度应力和/或客户操作之后一致地擦除数据。此外，通过在编程期间利用基本上高的栅极和漏极电压，编程时间保持较短，而不会降低电荷损失。提供了一种确定在编程和擦除周期期间单位操作的电荷损失的方法。然后利用循环和应力的电荷损耗来确定要编程到命令逻辑和状态机中的适当的增量VT。

58. 发明授权

US06442074B1 Tailored erase method using higher program VT and higher negative gate erase 有权
标题翻译：使用更高程序VT和更高的负栅极擦除进行定制擦除方法
公开(公告)号：US06442074B1
公开(公告)日：2002-08-27
申请号：US09795854
申请日：2001-02-28
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/344 , G11C16/3445 , G11C29/50
摘要： A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IO's together. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. This erase pulse that provides a substantially high electric field is selected to erase band to band currents for the entire array that are larger than can be supplied by drain pumps.
摘要翻译：用于编程和擦除双位存储器单元的存储器阵列的正常位的方法和系统通过以基本上高的delta VT和擦除脉冲进行编程来实现，该擦除脉冲为扇区1中的每个I / O提供基本上高的电场一次在第一个擦除脉冲之后，擦除验证程序在所有IO上一起执行。基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。选择提供基本上高的电场的擦除脉冲，以消除整个阵列的频带电流，其大于由排水泵提供的频带电流。

59. 发明授权

US06331953B1 Intelligent ramped gate and ramped drain erasure for non-volatile memory cells 有权
标题翻译：非易失性存储单元的智能斜坡栅极和斜坡漏极擦除
公开(公告)号：US06331953B1
公开(公告)日：2001-12-18
申请号：US09697813
申请日：2000-10-26
申请人： Janet S. Y. Wang , Narbeh Derhacobian , Daniel Sobek
发明人： Janet S. Y. Wang , Narbeh Derhacobian , Daniel Sobek
IPC分类号： G11C700
CPC分类号： G11C16/344 , G11C11/5671 , G11C16/0475 , G11C16/14 , G11C16/3445 , H01L29/7923
摘要： A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes: applying a voltage across the gate and the first region in accordance with a coarse erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region; and applying a voltage across the gate and the first region in accordance with a fine erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region.
摘要翻译：一种擦除存储单元的方法，该存储单元包括第一区域和第二区域以及通道之间的通道，以及包含第一电荷量的电荷捕获区域。该方法包括：根据粗略擦除电压序列施加跨栅极和第一区域的电压，使得第一电荷量的一部分从电荷捕获区域去除; 以及根据电压的精细擦除序列施加跨越栅极和第一区域的电压，使得第一电荷量的一部分从电荷捕获区域去除。

60. 发明授权

US06327183B1 Nonlinear stepped programming voltage 有权
标题翻译：非线性步进编程电压
公开(公告)号：US06327183B1
公开(公告)日：2001-12-04
申请号：US09480868
申请日：2000-01-10
申请人： Joseph G. Pawletko , K. Michael Han , Narbeh Derhacobian
发明人： Joseph G. Pawletko , K. Michael Han , Narbeh Derhacobian
IPC分类号： G11C700
CPC分类号： G11C5/147 , G11C16/12 , G11C16/3468
摘要： A voltage control circuit that narrows the distribution of threshold voltages of memory cells by using nonlinearly incremented programming voltages. To do so, the voltage control circuit applies to the memory cells a first program pulse of a first voltage, a second program pulse of a second voltage to the memory cell, and a third program pulse of a third voltage, where the difference between the third voltage and the second voltage is less than the difference between the second voltage and the first voltage.
摘要翻译：一种电压控制电路，其通过使用非线性递增的编程电压来缩小存储器单元的阈值电压的分布。为此，电压控制电路向存储器单元施加第一电压的第一编程脉冲，到存储单元的第二电压的第二编程脉冲和第三电压的第三编程脉冲，第三电压，第二电压小于第二电压和第一电压之间的差。

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