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51. 发明授权

US06437385B1 Integrated circuit capacitor 失效
标题翻译：集成电路电容
公开(公告)号：US06437385B1
公开(公告)日：2002-08-20
申请号：US09607094
申请日：2000-06-29
申请人： Claude L. Bertin , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10832 , H01L28/55 , H01L28/87 , H01L29/66181 , H01L29/945
摘要： Use of different materials for different conductive films forming plates or electrodes of one or more capacitors formed in a trench in a body of semiconductor materials allow connections to be made selectively to the plates. The films may be undercut by different etchants at respective connection apertures to avoid formation of connections or connections made by doped polysilicon of different conductivities forming connections to some plates of similarly doped polysilicon and blocking diode junctions with oppositely doped polysilicon. The blocking diodes may include a compensation implant to adjust reverse breakdown characteristics and provide transient and electrostatic discharge protection.
摘要翻译：对于形成在半导体材料体中的沟槽中的一个或多个电容器形成板或不同导电膜的不同材料的使用允许选择性地连接板。这些膜可能在相应的连接孔处被不同的蚀刻剂削弱，以避免由不同导电性的掺杂多晶硅形成的连接或连接形成连接到具有相反掺杂多晶硅的类似掺杂多晶硅和阻塞二极管结的某些平板。阻塞二极管可以包括补偿注入以调整反向击穿特性并提供瞬态和静电放电保护。

52. 发明授权

US06281731B1 Control of hysteresis characteristic within a CMOS differential receiver 有权
标题翻译：控制CMOS差分接收器内的滞后特性
公开(公告)号：US06281731B1
公开(公告)日：2001-08-28
申请号：US09428639
申请日：1999-10-27
申请人： John A. Fifield , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
发明人： John A. Fifield , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K3297
CPC分类号： H03K3/3565 , H03K3/02337
摘要： A differential receiver has a switching point accurately set according to a reference voltage, which switching point is dynamically modified, that is, dc hysteresis is provided, by a circuit internal to the differential receiver. Positioning of the resultant hysteresis characteristic about the reference signal is adjusted by establishing a backgate voltage differential between an input transistor and a reference transistor of the differential receiver. A switching circuit is also provided for controlling switching of a hysteresis circuit at the reference signal plus or minus a desired offset. The switching circuit is gated by an output signal of the input transistor.
摘要翻译：差分接收器具有根据参考电压精确设置的开关点，通过差分接收器内部的电路动态地修改切换点，即提供直流滞后。通过在差分接收器的输入晶体管和参考晶体管之间建立背栅电压差来调整所产生的关于参考信号的滞后特性的定位。还提供了一种开关电路，用于控制滞后电路在参考信号加或减所需偏移的切换。开关电路由输入晶体管的输出信号选通。

53. 发明授权

US6040991A SRAM memory cell having reduced surface area 失效
标题翻译：具有减小的表面积的SRAM存储单元
公开(公告)号：US6040991A
公开(公告)日：2000-03-21
申请号：US225074
申请日：1999-01-04
申请人： John J. Ellis-Monaghan , Wilbur D. Pricer
发明人： John J. Ellis-Monaghan , Wilbur D. Pricer
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： G11C11/412
摘要： A Static RAM cell having a reduced surface area. The Static RAM cell includes a pair of P channel transistors and a pair of N channel transistors connected as a bistable latch. A first common source connection of the latch is connected to a Write Bit terminal and the remaining source connections of the latch are connected to complementary bit lines. A word line addressing the latch is provided through the transistors connected to the Bit Lines having shared body contact which permits reading and writing to the latch. During a write mode, the word line is connected to a potential which renders transistors connected to the complementary bit lines conductive, while the write bit connected to a potential which renders the remaining transistors nonconducting. During a read operation, one of the remaining transistors are rendered conductive, and the word line renders the set of transistors connected to the Bit Lines conductive so that the bit Lines are charged from the respective nodes of the latch.
摘要翻译：具有减小的表面积的静态RAM单元。静态RAM单元包括一对P沟道晶体管和作为双稳态锁存器连接的一对N沟道晶体管。锁存器的第一个公共源极连接连接到写入位端，并且锁存器的其余源极连接连接到互补位线。通过连接到具有共享体接触的位线的晶体管提供寻址锁存器的字线，其允许读取和写入锁存器。在写入模式期间，字线连接到使连接到互补位线的晶体管导通的电位，而写入位连接到使剩余晶体管不导通的电位。在读取操作期间，剩余晶体管中的一个导通，并且字线使连接到位线的晶体管组导通，使得位线从锁存器的相应节点充电。

54. 发明授权

US5594883A Hierarchical data storage system employing contemporaneous transfer of designated data pages to long write and short read cycle memory 失效
标题翻译：分层数据存储系统采用同时传送指定的数据页到长写和短读周期内存
公开(公告)号：US5594883A
公开(公告)日：1997-01-14
申请号：US556671
申请日：1995-11-13
申请人： Wilbur D. Pricer
发明人： Wilbur D. Pricer
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F2212/2022
摘要： A method and system control approach for contemporaneous transfer of designated replacement pages from a main store to an associated memory having a write cycle 10.times. longer than a read cycle thereof (e.g. nonvolatile semiconductor memory). Each designated data page includes an associated home address within the nonvolatile semiconductor memory. The approach includes designating at least two data pages of the main store for transfer to the nonvolatile semiconductor memory; and upon occurrence of a predetermined condition, contemporaneously transferring the designated data pages from the main store to the nonvolatile semiconductor memory for writing into the nonvolatile semiconductor memory at their associated addresses. Preferably, the designated data pages are simultaneously written in the nonvolatile semiconductor memory subsequent to a simultaneous erase of their associated home addresses.
摘要翻译：一种方法和系统控制方法，用于将指定的替代页面从主存储器同时传送到具有比其读取周期长10倍（例如非易失性半导体存储器）的写入周期的关联存储器。每个指定的数据页包括在非易失性半导体存储器内的相关联的归属地址。该方法包括指定主存储器的至少两个数据页面以传送到非易失性半导体存储器; 并且在发生预定条件时，同时将指定的数据页从主存储转移到非易失性半导体存储器，以在其相关联的地址写入非易失性半导体存储器。优选地，在同时擦除其相关联的家庭地址之后，将指定的数据页同时写入非易失性半导体存储器。

55. 发明授权

US5409852A Method of Manufacturing three dimensional integrated device and circuit structures 失效
标题翻译：制造三维集成器件和电路结构的方法
公开(公告)号：US5409852A
公开(公告)日：1995-04-25
申请号：US71767
申请日：1993-07-21
申请人： Thomas B. Faure , Bernard S. Meyerson , Wilbur D. Pricer , Cecilia C. Smolinski
发明人： Thomas B. Faure , Bernard S. Meyerson , Wilbur D. Pricer , Cecilia C. Smolinski
IPC分类号： H01L21/20 , H01L21/31 , H01L27/00 , H01L27/06 , H01L21/265
CPC分类号： H01L27/0688
摘要： A set of three-dimensional structures and devices may be wired together to perform a wide variety of circuit functions such as SRAMs, DRAMs, ROMs and PLAs. Both N-Channel and P-Channel transistors can be made. The P-channel devices are fabricated conventionally in separate N-wells or, alteratively, they are constructed in a like manner to the array N-channel devices. N and P diffused wire can be electrically joined at polysilicon contacts.
摘要翻译：一组三维结构和器件可以连接在一起以执行各种各样的电路功能，例如SRAM，DRAM，ROM和PLA。可以制造N沟道和P沟道晶体管。 P沟道器件通常在单独的N阱中制造，或者替代地，它们以类似的方式构造到阵列N沟道器件。 N和P扩散线可以在多晶硅接触处电连接。

56. 发明授权

US5222109A Endurance management for solid state files 失效
标题翻译：固态文件的耐久性管理
公开(公告)号：US5222109A
公开(公告)日：1993-06-22
申请号：US635910
申请日：1990-12-28
申请人： Wilbur D. Pricer
发明人： Wilbur D. Pricer
IPC分类号： G06F12/16 , G01C22/02 , G11C16/02 , G11C17/00 , G11C29/00 , G11C29/04
CPC分类号： G11C29/765 , G01C22/02
摘要： A nonvolatile storage system including several data storage arrays; a counter storage array for storing values indicating the remaining useful life of each of the data storage arrays; and a device for controlling access to each of the data storage arrays as a function of the values stored in each counter array. The counter array has an appreciably longer useful life than any of the data storage arrays.

57. 发明授权

US5057450A Method for fabricating silicon-on-insulator structures 失效
标题翻译：绝缘体上硅结构的制造方法
公开(公告)号：US5057450A
公开(公告)日：1991-10-15
申请号：US678390
申请日：1991-04-01
申请人： Gary B. Bronner , Paul M. Fahey , Bernard S. Meyerson , Wilbur D. Pricer
发明人： Gary B. Bronner , Paul M. Fahey , Bernard S. Meyerson , Wilbur D. Pricer
IPC分类号： H01L21/762 , H01L21/306 , H01L21/308 , H01L21/763 , H01L21/764 , H01L27/12
CPC分类号： H01L21/3083 , H01L21/30604 , H01L21/763 , H01L21/764 , H01L21/76264 , H01L21/76289 , Y10S148/135
摘要： A fabrication method for forming SOI structures where perfect material is grown epitaxially on a substrate and then, through a series of selective etches and oxidations, an insulating layer is formed below the epitaxial silicon. In the method, low temperature epitaxial techniques are employed to grow a layered structure including a first layer p++ silicon on a substrate wafer, a layer of intrinsic silicon is then formed on the first p++ silicon layer, and a second layer of p++ silicon is formed on the intrinsic silicon layer, and a finally a layer of p-silicon is fabricated on top of the second p++ silicon layer. Grooves are formed through the p-layer, the second p++ silicon layer, the intrinsic silicon layer, and stopped in the first p++ silicon layer. An etch is then employed to remove the intrinsic layer long enough for the p++ silicon layer to be totally undercut, leaving an air gap between the two p++ silicon layers. An oxidation step is then performed to form a bottom insulator consisting of the oxidized first p++ silicon layer and on an upper insulator consisting of the oxidized second p++ silicon layer.

58. 发明授权

US4857766A BiMos input circuit 失效
标题翻译： BiMos输入电路
公开(公告)号：US4857766A
公开(公告)日：1989-08-15
申请号：US114973
申请日：1987-10-30
申请人： Wilbur D. Pricer , Francis W. Wiedman
发明人： Wilbur D. Pricer , Francis W. Wiedman
IPC分类号： H03K5/02 , H03K19/0175 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/017518
摘要： An ECL input circuit which receives an ECL input signal and which generates, in response to the input signal, a CMOS-compatible output signal. The input circuit includes a bipolar transistor, having its emitter region adapted to receive the ECL input signal, having its collector region coupled to a first current source, and having its base region connected to a second current source. The circuit further includes an output circuit which is coupled to the collector region of the bipolar transistor for providing the CMOS-compatible signal.

59. 发明授权

US4322823A Storage system having bilateral field effect transistor personalization 失效
标题翻译：具有双向场效应晶体管个性化的存储系统
公开(公告)号：US4322823A
公开(公告)日：1982-03-30
申请号：US126636
申请日：1980-03-03
申请人： Wilbur D. Pricer , James E. Selleck
发明人： Wilbur D. Pricer , James E. Selleck
IPC分类号： G11C17/00 , G11C11/34 , G11C11/40 , G11C11/56 , G11C17/12 , H01L21/822 , H01L21/8246 , H01L27/04 , H01L27/112 , H01L29/10
CPC分类号： G11C11/34 , G11C11/40 , G11C11/56 , G11C11/5692
摘要： A storage system, such as a read only memory, is provided which includes field effect transistors each having first and second spaced apart diffusion regions of a given conductivity and a gate electrode, with at least one of the two diffusion regions of selected transistors having a third diffusion adjacent to one of the first and second diffusion regions under the gate electrodes to provide a higher voltage threshold for the gate electrode to one diffusion than for the gate electrode to the other of the two diffusions. A voltage is applied to the first diffusion having a polarity and magnitude sufficient to neutralize or eliminate the effects of the higher threshold during a first time period and the current flowing between the first and second diffusions is sensed. During a second period of time the voltage is applied to the second diffusion and the current flow between the first and second diffusions is again sensed. In this manner two cells or bits of information are stored in each transistor, one at the first diffusion and one at the second diffusion. Multilevel storing may also be employed by establishing one of more than two predetermined voltage thresholds at each of the first and second diffusions.
摘要翻译：提供了诸如只读存储器的存储系统，其包括场效应晶体管，每个场效应晶体管具有给定电导率的第一和第二间隔扩散区域和栅电极，所选择的晶体管的两个扩散区域中的至少一个具有邻近栅极电极下方的第一和第二扩散区域之一的第三扩散，以使栅电极相对于两个扩散中的另一个扩散的栅电极的一个扩散提供较高的电压阈值。电压施加到具有足以中和或消除在第一时间段期间较高阈值的影响的极性和幅度，并且感测在第一和第二扩散之间流动的电流的第一扩散。在第二时间段期间，电压被施加到第二扩散，并且再次感测在第一和第二扩散之间的电流。以这种方式，在每个晶体管中存储两个单元或位信息，一个在第一扩散处，一个在第二扩散处。也可以通过在第一和第二扩散中的每一个处建立多于两个的预定电压阈值之一来采用多电平存储。

60. 发明授权

US4160275A Accessing arrangement for memories with small cells 失效
标题翻译：使用小电池存储器的安装
公开(公告)号：US4160275A
公开(公告)日：1979-07-03
申请号：US892605
申请日：1978-04-03
申请人： Hsing-San Lee , Wilbur D. Pricer , Norbert G. Vogl, Jr.
发明人： Hsing-San Lee , Wilbur D. Pricer , Norbert G. Vogl, Jr.
IPC分类号： G11C11/401 , G11C11/35 , G11C11/4097 , G11C11/24 , G11C7/06
CPC分类号： G11C11/35 , G11C11/4097
摘要： A merged charge memory system is provided having an accessing arrangement wherein each of the word lines of the memory array is divided into a plurality of segments with cells associated only with a selected one or a portion of the segments being coupled at any particular time to bit driving and sensing means. Thus, only relatively few sense amplifiers compared with the number of bits per word of the array are required to handle all of the cells of the array. More particularly, in the merged charge memory system of the present invention, the flow of charges from charge source means is released only to the cells of the selected word segment or segments which are simultaneously coupled to bit driving and sensing means via associated bit/sense lines.
摘要翻译：合并的电荷存储器系统具有访问布置。存储器阵列的每个字线被分成多个段，其中单元仅与选定的一个或一部分段相关联，在任何特定时间被耦合到位驱动和感测设备。因此，仅需要相对较少的读出放大器与阵列的每个字的位数相比较来处理阵列的所有单元。来自电荷源的电荷流仅释放到所选择的字段的单元或通过相关联/感测线同时耦合到位驱动和感测装置的段。 -

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