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1. 发明授权

US06249029B1 Device method for enhanced avalanche SOI CMOS 失效
标题翻译：增强型雪崩SOI CMOS器件方法
公开(公告)号：US06249029B1
公开(公告)日：2001-06-19
申请号：US09320595
申请日：1999-05-26
申请人： Andres Bryant , William F. Clark , John J. Ellis-Monaghan , Edward P. Maciejewski , Edward J. Nowak , Wilbur D. Pricer , Minh H. Tong
发明人： Andres Bryant , William F. Clark , John J. Ellis-Monaghan , Edward P. Maciejewski , Edward J. Nowak , Wilbur D. Pricer , Minh H. Tong
IPC分类号： H01L2976
CPC分类号： H01L29/7841 , H01L27/1203
摘要： A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.
摘要翻译：用于SOI CMOS中的FET的器件设计，其被设计用于当FET导通时增强通过器件的电流的雪崩倍增，并且当FET关闭时去除体电荷。 FET具有电浮动体并且与衬底基本上电隔离。本发明提供了将FET的浮体耦合到FET的源极的高电阻路径，使得该电阻器使得该器件能够充当用于有源开关目的的浮动体并且作为待机模式中的接地体以减少漏电流。高电阻路径具有至少1MΩ的电阻，并且包括通过使用分离多晶硅工艺制造的多晶硅电阻器，其中掩埋接触掩模在第一多晶硅层中打开孔，以允许第二多晶硅层接触基板。

2. 发明授权

US6040991A SRAM memory cell having reduced surface area 失效
标题翻译：具有减小的表面积的SRAM存储单元
公开(公告)号：US6040991A
公开(公告)日：2000-03-21
申请号：US225074
申请日：1999-01-04
申请人： John J. Ellis-Monaghan , Wilbur D. Pricer
发明人： John J. Ellis-Monaghan , Wilbur D. Pricer
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： G11C11/412
摘要： A Static RAM cell having a reduced surface area. The Static RAM cell includes a pair of P channel transistors and a pair of N channel transistors connected as a bistable latch. A first common source connection of the latch is connected to a Write Bit terminal and the remaining source connections of the latch are connected to complementary bit lines. A word line addressing the latch is provided through the transistors connected to the Bit Lines having shared body contact which permits reading and writing to the latch. During a write mode, the word line is connected to a potential which renders transistors connected to the complementary bit lines conductive, while the write bit connected to a potential which renders the remaining transistors nonconducting. During a read operation, one of the remaining transistors are rendered conductive, and the word line renders the set of transistors connected to the Bit Lines conductive so that the bit Lines are charged from the respective nodes of the latch.
摘要翻译：具有减小的表面积的静态RAM单元。静态RAM单元包括一对P沟道晶体管和作为双稳态锁存器连接的一对N沟道晶体管。锁存器的第一个公共源极连接连接到写入位端，并且锁存器的其余源极连接连接到互补位线。通过连接到具有共享体接触的位线的晶体管提供寻址锁存器的字线，其允许读取和写入锁存器。在写入模式期间，字线连接到使连接到互补位线的晶体管导通的电位，而写入位连接到使剩余晶体管不导通的电位。在读取操作期间，剩余晶体管中的一个导通，并且字线使连接到位线的晶体管组导通，使得位线从锁存器的相应节点充电。

3. 发明授权

US5959335A Device design for enhanced avalanche SOI CMOS 有权
标题翻译：增强型雪崩SOI CMOS器件设计
公开(公告)号：US5959335A
公开(公告)日：1999-09-28
申请号：US159307
申请日：1998-09-23
申请人： Andres Bryant , William F. Clark , John J. Ellis-Monaghan , Edward P. Maciejewski , Edward J. Nowak , Wilbur D. Pricer , Minh H. Tong
发明人： Andres Bryant , William F. Clark , John J. Ellis-Monaghan , Edward P. Maciejewski , Edward J. Nowak , Wilbur D. Pricer , Minh H. Tong
IPC分类号： H01L27/06 , H01L21/8234 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7841 , H01L27/1203
摘要： A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.
摘要翻译：用于SOI CMOS中的FET的器件设计，其被设计用于当FET导通时增强通过器件的电流的雪崩倍增，并且当FET关闭时去除体电荷。 FET具有电浮动体并且与衬底基本上电隔离。本发明提供了将FET的浮体耦合到FET的源极的高电阻路径，使得该电阻器使得该器件能够充当用于有源开关目的的浮动体并且作为待机模式中的接地体以减少漏电流。高电阻路径具有至少1MΩ的电阻，并且包括通过使用分离多晶硅工艺制造的多晶硅电阻器，其中掩埋接触掩模在第一多晶硅层中打开孔，以允许第二多晶硅层接触基板。

4. 发明授权

US08927357B2 Junction field-effect transistor with raised source and drain regions formed by selective epitaxy 有权
标题翻译：通过选择性外延形成的具有升高的源极和漏极区的结场场效应晶体管
公开(公告)号：US08927357B2
公开(公告)日：2015-01-06
申请号：US13294731
申请日：2011-11-11
申请人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L21/337 , H01L29/10 , H01L27/06 , H01L29/66 , H01L29/737 , H01L29/808 , H01L29/165 , H01L29/08
CPC分类号： H01L29/8086 , G06F17/5045 , H01L27/0623 , H01L29/0817 , H01L29/0826 , H01L29/1004 , H01L29/1058 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66242 , H01L29/66893 , H01L29/66901 , H01L29/732 , H01L29/7375 , H01L29/808
摘要： Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.
摘要翻译：结型场效应晶体管，用于制造结型场效应晶体管的方法，以及结型场效应晶体管的设计结构。结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

5. 发明授权

US08890557B2 Built-in self-test method and structure 有权
标题翻译：内置自检方法和结构
公开(公告)号：US08890557B2
公开(公告)日：2014-11-18
申请号：US13443450
申请日：2012-04-10
申请人： Yoba Amoah , John J. Ellis-Monaghan , Roger C. Kuo , Molly J. Leitch , Zhihong Zhang
发明人： Yoba Amoah , John J. Ellis-Monaghan , Roger C. Kuo , Molly J. Leitch , Zhihong Zhang
IPC分类号： G01R31/3187
CPC分类号： G01R31/318511 , G01R31/2856 , G11C29/006 , G11C29/12 , G11C2029/1206
摘要： A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST.
摘要翻译：一种半导体晶片的测试方法及相关结构。在各种实施例中，一种方法包括：将探针放置在半导体晶片上的第一芯片上; 测试划线自动内置自检（ABIST）为第一芯片寻找故障; 响应于确定第一芯片的ABIST而对半导体晶片上的后续芯片进行随后的划线ABIST的逐步测试不表示故障; 将探针点移动到随后的芯片，并且响应于确定随后芯片的ABIST指示故障，重新测试随后的划线ABIST; 以及响应于确定随后的scribiline的重新测试，测试另一后续划线ABIST用于半导体晶片上的另外的后续芯片，ABIST不指示后续划线ABIST中的故障。

6. 发明授权

US08836835B2 Pixel sensor cell with hold node for leakage cancellation and methods of manufacture and design structure 有权
标题翻译：具有保护节点的像素传感器单元用于泄漏消除，以及制造和设计结构的方法
公开(公告)号：US08836835B2
公开(公告)日：2014-09-16
申请号：US12897295
申请日：2010-10-04
申请人： James W. Adkisson , John J. Ellis-Monaghan , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Richard J. Rassel
IPC分类号： H04N5/335 , H04N5/359 , H01L27/146 , H04N5/3745
CPC分类号： H04N5/3595 , H01L27/14603 , H01L27/14609 , H04N5/3532 , H04N5/359 , H04N5/3745 , H04N5/378
摘要： A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided. A pixel array includes one or more reference pixel sensor cells dispersed locally throughout active light sensing regions. The one or more reference pixel sensor cells provides a reference signal used to correct for photon generated leakage signals which vary by locality within the active light sensing regions.
摘要翻译：提供了具有用于泄漏消除的保持节点的参考像素传感器单元（例如，全局快门），制造方法和设计结构。像素阵列包括在有源光感测区域局部分散的一个或多个参考像素传感器单元。一个或多个参考像素传感器单元提供用于校正由于有源光感测区域内的局部性而变化的光子产生的泄漏信号的参考信号。

7. 发明授权

US08791712B2 3-dimensional integrated circuit testing using MEMS switches with tungsten cone contacts 有权
标题翻译：使用具有钨锥触点的MEMS开关的三维集成电路测试
公开(公告)号：US08791712B2
公开(公告)日：2014-07-29
申请号：US13364345
申请日：2012-02-02
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G01R1/067
CPC分类号： G01R1/06727 , B81B2203/0118 , B81C1/00111 , G01R1/06738 , G01R1/06744 , G01R1/07342 , G01R3/00 , H01L21/76804 , H01L21/76885 , H01L22/14 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).
摘要翻译：一种用于测试多层三维集成电路（IC）的测试系统，其中临时连接两个独立的IC电路层以实现功能性，包括具有三维IC的第一部分的被测芯片，以及测试探针芯片，其具有第三部分的IC和微机电系统（MEMS）开关，其选择性地完成第一IC层中的第三部分的第三部分之间的功能电路和第二部分内的电路的三维IC在第二IC层中。 MEMS开关包括钨（W）锥形触点，其使得被测芯片的电路和测试探针芯片之间的选择性电接触，并且使用梯度硼磷硅酸盐玻璃（BPSG）的模板形成。

8. 发明申请

US20140183753A1 FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES 有权
标题翻译：制造POLYSILICON MOS器件和被动ESD器件
公开(公告)号：US20140183753A1
公开(公告)日：2014-07-03
申请号：US13733243
申请日：2013-01-03
申请人： John J. Ellis-Monaghan , Michael J. Hauser , Zhong-Xiang He , Junjun Li , Xuefeng Liu , Anthony K. Stamper
发明人： John J. Ellis-Monaghan , Michael J. Hauser , Zhong-Xiang He , Junjun Li , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L27/04 , H01L21/36
CPC分类号： B81C1/00301 , B81B7/007 , B81B2207/094 , B81C1/00246 , B81C2203/0714 , B81C2203/0742 , H01L21/84 , H01L27/1203
摘要： A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.
摘要翻译：描述了半导体制造，其中在BEOL工艺中同时制造MOS器件和MEMS器件。沉积并蚀刻硅层以形成用于MOS器件的硅膜和用于MEMS器件的下硅牺牲膜。导电层沉积在硅层顶部并被蚀刻以形成金属栅极和第一上电极。介电层沉积在导电层顶上，并且通孔形成在电介质层中。另一个导电层沉积在电介质层顶上并被蚀刻以形成用于MOS器件的第二上电极和三个金属电极。另一硅层沉积在另一导电层的顶上，并被蚀刻以形成用于MEMS器件的上硅牺牲膜。然后通过排气孔去除上部和下部硅牺牲膜。

9. 发明授权

US08647913B2 Image sensor, method and design structure including non-planar reflector 失效
标题翻译：图像传感器，方法和设计结构包括非平面反射器
公开(公告)号：US08647913B2
公开(公告)日：2014-02-11
申请号：US13614210
申请日：2012-09-13
申请人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
发明人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
IPC分类号： H01L27/00
CPC分类号： H01L27/14643 , H01L27/14621 , H01L27/14625 , H01L27/1464 , H01L27/14683 , H01L27/14685
摘要： A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate.
摘要翻译：固态图像传感器，制造固态图像传感器的方法和用于制造固态图像传感器结构的设计结构包括依次包括感光区域的基板。还包括在固态图像传感器内的非平面反射器层位于感光区域和基板的与感光区域和基板的入射辐射侧相对的一侧上。非平面反射器层被成形和定位成将未捕获的入射辐射反射回光敏区域，同时避免与衬底内横向分离的附加光敏区域的光学串扰。

10. 发明申请

US20130105941A1 SEMICONDUCTOR DEVICE INCLUDING IN WAFER INDUCTORS, RELATED METHOD AND DESIGN STRUCTURE 有权
标题翻译：包括波导电感的半导体器件，相关方法和设计结构
公开(公告)号：US20130105941A1
公开(公告)日：2013-05-02
申请号：US13282123
申请日：2011-10-26
申请人： Daniel S. Vanslette , John J. Ellis-Monaghan , Renata A. Camillo-Castillo , Robert M. Rassel
发明人： Daniel S. Vanslette , John J. Ellis-Monaghan , Renata A. Camillo-Castillo , Robert M. Rassel
IPC分类号： H01L23/48 , G06F17/50 , H01L21/02
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/5227 , H01L27/016 , H01L27/0694 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first set of trenches formed in a first surface of the substrate; a second set of trenches formed in a second surface of the substrate; and at least one through silicon via connecting the first set of trenches and the second set of trenches.
摘要翻译：一种集成电路（IC）及其制造方法。在一个实施例中，IC包括：衬底; 形成在所述基板的第一表面中的第一组沟槽; 形成在所述基板的第二表面中的第二组沟槽; 以及通过连接第一组沟槽和第二组沟槽的至少一个穿硅。

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