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51. 发明申请

US20050037548A1 SOI field effect transistor element having a recombination region and method of forming same 审中-公开
标题翻译：具有复合区域的SOI场效应晶体管元件及其形成方法
公开(公告)号：US20050037548A1
公开(公告)日：2005-02-17
申请号：US10949089
申请日：2004-09-24
申请人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
发明人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
IPC分类号： H01L21/336 , H01L29/786 , H01L21/00
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78612 , H01L29/78684
摘要： An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.
摘要翻译：公开了SOI晶体管元件及其制造方法，其中通过在有源晶体管区域内包含具有轻微晶格失配的区域来产生高浓度的固定点缺陷。在一个特定实施例中，由于在对晶体管元件进行热处理时放松硅锗层的应变，在有源区域中提供了具有高浓度点缺陷的硅锗层。由于点缺陷，复合率显着增加，从而减少存储在有源区域中的带电载流子数量。

52. 发明授权

US06491799B1 Method for forming a thin dielectric layer 失效
标题翻译：薄介电层的形成方法
公开(公告)号：US06491799B1
公开(公告)日：2002-12-10
申请号：US09766738
申请日：2001-01-22
申请人： Frederick N. Hause , Karsten Wieczorek , Manfred Horstmann
发明人： Frederick N. Hause , Karsten Wieczorek , Manfred Horstmann
IPC分类号： C23C1434
CPC分类号： C23C14/10 , C23C14/3407 , C23C14/3471
摘要： The method disclosed herein comprises initially providing a tool comprised of a process chamber, a lid above the process chamber, an RF coil for assisting in generating a plasma in the chamber, a substrate support, and a power supply coupled to the substrate support. The method continues with the step of positioning a substrate in the tool adjacent the substrate support, introducing a noble gas into the chamber, and forming a layer of material above the substrate by sputtering the lid material by performing at least the following steps: applying approximately 200-300 watts of power to the RF coil at a frequency of approximately 400 KHz and applying approximately 20-60 watts of power to the substrate at a frequency of approximately 13.56 MHz.
摘要翻译：本文公开的方法包括最初提供一种工具，其包括处理室，处理室上方的盖，用于辅助在室中产生等离子体的RF线圈，衬底支撑件和耦合到衬底支撑件的电源。该方法继续以下步骤：将衬底定位在邻近衬底支撑件的工具中，将惰性气体引入腔室中，以及通过至少执行以下步骤溅射盖材料在衬底上方形成材料层：近似施加以大约400KHz的频率向RF线圈施加200-300瓦的功率，并以大约13.56MHz的频率向衬底施加大约20-60瓦的功率。

53. 发明授权

US06218250B1 Method and apparatus for minimizing parasitic resistance of semiconductor devices 有权
标题翻译：用于最小化半导体器件的寄生电阻的方法和装置
公开(公告)号：US06218250B1
公开(公告)日：2001-04-17
申请号：US09324183
申请日：1999-06-02
申请人： Frederick N. Hause , Karsten Wieczorek , Manfred Horstmann
发明人： Frederick N. Hause , Karsten Wieczorek , Manfred Horstmann
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/26586 , H01L21/28518 , H01L29/456 , H01L29/4933
摘要： A semiconductor device includes a substrate, a gate structure, a plurality of sidewall spacers, and a plurality of first silicide layers. The gate structure is positioned above the substrate. The plurality of sidewall spacers are positioned adjacent to the gate structure. The first silicide layers are positioned in the substrate and have first ends that extend underneath the sidewall spacers. A method for forming a semiconductor device includes forming a gate structure above a substrate. A plurality of sidewall spacers are formed adjacent the gate structure. An implant material is disposed into the substrate using a tilted implantation process that is adapted to form first implant regions in the substrate. The implant regions have first ends that extend underneath the sidewall spacers by a first distance.
摘要翻译：半导体器件包括衬底，栅极结构，多个侧壁间隔物和多个第一硅化物层。栅极结构位于衬底上方。多个侧壁间隔件邻近门结构定位。第一硅化物层位于衬底中并且具有在侧壁间隔物下方延伸的第一端。一种形成半导体器件的方法包括在衬底上形成栅极结构。在栅极结构附近形成多个侧壁间隔物。使用倾斜的注入工艺将注入材料设置到衬底中，所述倾斜注入工艺适于在衬底中形成第一注入区域。植入区域具有在侧壁间隔物下方延伸第一距离的第一端。

54. 发明授权

US6133124A Device improvement by source to drain resistance lowering through undersilicidation 有权
标题翻译：器件通过源极降低漏极电阻降低硅芯片
公开(公告)号：US6133124A
公开(公告)日：2000-10-17
申请号：US245951
申请日：1999-02-05
申请人： Manfred Horstmann , Karsten Wieczorek , Frederick N. Hause
发明人： Manfred Horstmann , Karsten Wieczorek , Frederick N. Hause
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/425 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： Various methods of fabricating a silicide layer, and devices incorporating the same are provided. In one aspect, a method of fabricating a silicide layer on a substrate is provided. The method includes the steps of damaging the crystal structure of a portion of the substrate positioned beneath the spacer and depositing a layer of metal on the substrate. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer, whereby a portion of the silicide layer extends laterally beneath the spacer. Any unreacted metal is removed. The method enables fabrication of silicide layers with substantial lateral encroachment into LDD structures, resulting in lower possible source-to-drain resistance and enhanced performance for transistors.
摘要翻译：提供了制造硅化物层的各种方法，以及包含其的装置。一方面，提供了在基板上制造硅化物层的方法。该方法包括以下步骤：损坏位于间隔物下方的衬底的一部分的晶体结构并在衬底上沉积金属层。加热金属层和衬底以使金属与衬底反应并形成硅化物层，由此硅化物层的一部分横向延伸在衬垫下方。任何未反应的金属被去除。该方法能够制造具有大量横向侵入LDD结构的硅化物层，导致晶体管的可能的源极 - 漏极电阻和增强的性能。

55. 发明授权

US07745334B2 Technique for locally adapting transistor characteristics by using advanced laser/flash anneal techniques 有权
标题翻译：通过使用先进的激光/闪光退火技术来局部适应晶体管特性的技术
公开(公告)号：US07745334B2
公开(公告)日：2010-06-29
申请号：US11736939
申请日：2007-04-18
申请人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
发明人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/268 , H01L21/823807 , H01L27/11 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.
摘要翻译：通过对诸如硅化镍之类的金属硅化物形成进行诸如激光退火，闪光退火等复杂的退火技术，可以显着地减少诸如SRAM通孔之类的敏感器件区域中的硅化镍缺陷的风险。此外，可以以高度局部化的方式执行掺杂剂的激活，使得当激活和再结晶漏极和源极区域时，可以避免栅极绝缘层的过度损坏。

56. 发明授权

US06620718B1 Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device 有权
标题翻译：在半导体器件的栅电极和源极/漏极区上形成金属硅化物区域的方法
公开(公告)号：US06620718B1
公开(公告)日：2003-09-16
申请号：US09557713
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L213205
CPC分类号： H01L29/66507 , H01L29/66545
摘要： The present invention is directed to a method of forming metal silicide regions on a gate electrode (23) and on the source/drain regions (25) of a semiconductor device (100). In one illustrative embodiment, the method comprises forming a gate stack (17) above a semiconducting substrate (20), the gate stack (17) being comprised of a gate electrode (23) and a protective layer (24), forming a plurality of source/drain regions (25) in the substrate (20), and forming a first metal silicide region (28) above each of the source/drain regions (25). The method further comprises removing the protective layer (24) from above the gate electrode (23) and forming a second metal silicide region (31) above the gate electrode (23).
摘要翻译：本发明涉及一种在半导体器件（100）的栅电极（23）和源/漏区（25）上形成金属硅化物区的方法。在一个说明性实施例中，该方法包括在半导体衬底（20）上方形成栅极叠层（17），栅叠层（17）由栅电极（23）和保护层（24）组成，形成多个源极/漏极区（25），并且在源极/漏极区（25）之上形成第一金属硅化物区（28）。该方法还包括从栅电极（23）上方去除保护层（24），并在栅电极（23）上方形成第二金属硅化物区域（31）。

57. 发明申请

US20080081471A1 TECHNIQUE FOR LOCALLY ADAPTING TRANSISTOR CHARACTERISTICS BY USING ADVANCED LASER/FLASH ANNEAL TECHNIQUES 有权
标题翻译：使用先进激光/闪光技术的局部适应晶体管特性的技术
公开(公告)号：US20080081471A1
公开(公告)日：2008-04-03
申请号：US11736939
申请日：2007-04-18
申请人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
发明人： Patrick Press , Karla Romero , Martin Trentzsch , Karsten Wieczorek , Thomas Feudel , Markus Lenski , Rolf Stephan
IPC分类号： H01L21/44
CPC分类号： H01L21/268 , H01L21/823807 , H01L27/11 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.
摘要翻译：通过对诸如硅化镍之类的金属硅化物形成进行诸如激光退火，闪光退火等复杂的退火技术，可以显着地减少诸如SRAM通孔之类的敏感器件区域中的硅化镍缺陷的风险。此外，可以以高度局部化的方式执行掺杂剂的激活，使得当激活和再结晶漏极和源极区域时，可以避免栅极绝缘层的过度损坏。

58. 发明授权

US06306698B1 Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same 有权
标题翻译：具有栅电极和源/漏区以上的不同厚度的金属硅化物区域的半导体器件及其制造方法
公开(公告)号：US06306698B1
公开(公告)日：2001-10-23
申请号：US09558963
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L21336
CPC分类号： H01L29/66507
摘要： The present invention is directed to a semiconductor device (100) having enhanced electrical performance characteristics, and a method of making such a device. In one illustrative embodiment, the semiconductor device (100) is comprised of a polysilicon gate electrode (104) positioned above a gate insulation layer (105), a plurality of source/drain regions (109) formed in a semiconducting substrate (101), a first metal silicide region (111A) positioned above the gate electrode (104), a second metal silicide region (107) positioned above each of the source/drain regions (109), wherein the first metal silicide region (111A) is approximately 2-10 times thicker than each of the second metal silicide regions (107). In one illustrative embodiment, the inventive method disclosed herein comprises forming a first layer of a refractory metal (110) above a layer of polysilicon (104), and converting the refractory metal layer (110) to a metal suicide layer (111), and patterning the metal silicide layer (111) and the gate electrode layer (104) to form a metal silicide region (111A) above the gate electrode (104). The method further comprises forming a plurality of source/drain regions (109) in the substrate (101), forming a second layer comprised of a refractory metal above at least the gate stack (122) and the source/drain regions (109). The method concludes with converting at least a portion of the second layer of refractory metal to a second metal silicide region above each of the source/drain regions (109).
摘要翻译：本发明涉及具有增强的电气性能特性的半导体器件（100）以及制造这种器件的方法。在一个说明性实施例中，半导体器件（100）由位于栅极绝缘层（105）上方的多晶硅栅电极（104），形成在半导体衬底（101）中的多个源极/漏极区域（109）位于栅电极（104）上方的第一金属硅化物区（111A），位于源极/漏极区（109）之上的第二金属硅化物区（107），其中第一金属硅化物区（111A）约为2 比第二金属硅化物区域（107）的厚度大10〜10倍。在一个示例性实施例中，本文公开的本发明的方法包括在多晶硅层（104）上方形成难熔金属（110）的第一层，并将难熔金属层（110）转化为金属硅化物层（111），以及图案化金属硅化物层（111）和栅电极层（104）以在栅电极（104）上方形成金属硅化物区域（111A）。该方法还包括在衬底（101）中形成多个源极/漏极区（109），在至少栅极堆叠（122）和源极/漏极区（109）之上形成由难熔金属组成的第二层。该方法的结论是将难熔金属的第二层的至少一部分转换成源极/漏极区域（109）之上的第二金属硅化物区域。

59. 发明授权

US06423634B1 Method of forming low resistance metal silicide region on a gate electrode of a transistor 有权
标题翻译：在晶体管的栅电极上形成低电阻金属硅化物区域的方法
公开(公告)号：US06423634B1
公开(公告)日：2002-07-23
申请号：US09557697
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518 , H01L29/66545
摘要： In one embodiment, a protective layer is formed on the top surface of the gate electrode of a transistor device prior to the formation of low resistance metal silicide regions on the drain and source regions. The protective layer prevents the simultaneous formation of a metal silicide region on the gate electrode. Thereafter, a process layer is formed above the source/drain regions and the cover layer that is positioned above the gate electrode. Next, a surface of the process layer is planarized to expose the cover layer, and the cover layer is removed. Then, a metal silicide region is formed above the gate electrode by depositing a layer of refractory metal and performing at least one anneal process.
摘要翻译：在一个实施例中，在漏极和源极区域上形成低电阻金属硅化物区域之前，在晶体管器件的栅电极的顶表面上形成保护层。保护层防止在栅电极上同时形成金属硅化物区域。此后，在位于栅电极上方的源极/漏极区域和覆盖层之上形成处理层。接下来，将处理层的表面平坦化以露出覆盖层，并且去除覆盖层。然后，通过沉积难熔金属层并进行至少一个退火工艺，在栅电极上方形成金属硅化物区域。

60. 发明授权

US06268257B1 Method of forming a transistor having a low-resistance gate electrode 有权
标题翻译：形成具有低电阻栅电极的晶体管的方法
公开(公告)号：US06268257B1
公开(公告)日：2001-07-31
申请号：US09557714
申请日：2000-04-25
申请人： Karsten Wieczorek , Michael Raab , Rolf Stephan
发明人： Karsten Wieczorek , Michael Raab , Rolf Stephan
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L21/28247 , H01L29/6659
摘要： A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance portion in the gate electrode, for example, a thick gate silicide for supporting low gate delays by minimizing the gate resistance, and a thin low-resistance portion in the drain and source in order to meet the requirements for shallow junction integration. Moreover, a transistor is disclosed having a low-resistance gate electrode portion, the composition of which is different from the low-resistance portion of the drain and source.
摘要翻译：公开了一种方法，其中晶体管的栅电极的低电阻部分形成为独立于在漏极和源极区域中形成低电阻部分。因此，该器件在栅电极中具有厚的低电阻部分，例如，通过最小化栅极电阻来支持低栅极延迟的厚栅极硅化物，以及漏极和源极中的薄的低电阻部分，以便满足浅结合整合的要求。此外，公开了一种具有低电阻栅极电极部分的晶体管，其组成不同于漏极和源极的低电阻部分。

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