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1. 发明授权

US06812074B2 SOI field effect transistor element having a recombination region and method of forming same 有权
公开(公告)号：US06812074B2
公开(公告)日：2004-11-02
申请号：US10391255
申请日：2003-03-18
申请人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
发明人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
IPC分类号： H01L21339
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78612 , H01L29/78684 , Y10S438/933 , Y10S438/938
摘要： An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

2. 发明授权

US06754553B2 Implant monitoring using multiple implanting and annealing steps 失效
标题翻译：使用多个植入和退火步骤的植入物监测
公开(公告)号：US06754553B2
公开(公告)日：2004-06-22
申请号：US09820033
申请日：2001-03-28
申请人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
发明人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
IPC分类号： G06F1900
CPC分类号： H01L22/10 , H01J2237/30433 , H01J2237/31701 , H01L21/26506 , H01L21/2658
摘要： Test wafer consumption is a significant contributor to overall cost of manufacturing in semiconductor industry due to scrapping the test wafers after one monitoring of implantation parameters. This invention provides a method to reuse the same test wafer for monitoring the implantation parameters more than once. This method comprises the possibility of implanting the same implant species together with identical implanting and annealing conditions as well as of implanting a broad variety of implant species together with varying implanting and annealing conditions. Therefore, this invention helps to significantly reduce the number of test wafers consumed in the implant-area.
摘要翻译：测试晶片消耗是半导体工业制造总体成本的重要因素，因为在一次监测植入参数之后报废测试晶片。本发明提供一种重复使用相同测试晶片多于一次来监测注入参数的方法。该方法包括以相同的植入和退火条件以及植入各种植入物种以及不同的植入和退火条件一起植入相同植入物种的可能性。因此，本发明有助于显着减少在植入区域中消耗的测试晶片的数量。

3. 发明申请

US20050037548A1 SOI field effect transistor element having a recombination region and method of forming same 审中-公开
标题翻译：具有复合区域的SOI场效应晶体管元件及其形成方法
公开(公告)号：US20050037548A1
公开(公告)日：2005-02-17
申请号：US10949089
申请日：2004-09-24
申请人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
发明人： Karsten Wieczorek , Manfred Horstmann , Christian Krueger
IPC分类号： H01L21/336 , H01L29/786 , H01L21/00
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78612 , H01L29/78684
摘要： An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.
摘要翻译：公开了SOI晶体管元件及其制造方法，其中通过在有源晶体管区域内包含具有轻微晶格失配的区域来产生高浓度的固定点缺陷。在一个特定实施例中，由于在对晶体管元件进行热处理时放松硅锗层的应变，在有源区域中提供了具有高浓度点缺陷的硅锗层。由于点缺陷，复合率显着增加，从而减少存储在有源区域中的带电载流子数量。

4. 发明授权

US07955937B2 Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors 有权
标题翻译：包括SOI晶体管和体晶体管的半导体器件的制造方法
公开(公告)号：US07955937B2
公开(公告)日：2011-06-07
申请号：US11560896
申请日：2006-11-17
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
IPC分类号： H01L21/331
CPC分类号： H01L21/823481 , H01L21/76243 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.
摘要翻译：通过在其它基于SOI的CMOS电路的敏感RAM区域中形成块状晶体管，可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除可能通常通过提供增加的晶体管宽度的晶体管或通过提供身体纽带来考虑。因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

5. 发明申请

US20070228377A1 SEMICONDUCTOR DEVICE COMPRISING SOI TRANSISTORS AND BULK TRANSISTORS AND A METHOD OF FORMING THE SAME 有权
标题翻译：包含SOI晶体管和块晶体管的半导体器件及其形成方法
公开(公告)号：US20070228377A1
公开(公告)日：2007-10-04
申请号：US11560896
申请日：2006-11-17
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
IPC分类号： H01L29/76 , H01L21/84
CPC分类号： H01L21/823481 , H01L21/76243 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.
摘要翻译：通过在其它基于SOI的CMOS电路的敏感RAM区域中形成块状晶体管，可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除可能通常通过提供增加的晶体管宽度的晶体管或通过提供身体纽带来考虑。因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

6. 发明授权

US07226859B2 Method of forming different silicide portions on different silicon-containing regions in a semiconductor device 有权
标题翻译：在半导体器件中在不同含硅区域上形成不同硅化物部分的方法
公开(公告)号：US07226859B2
公开(公告)日：2007-06-05
申请号：US10282720
申请日：2002-10-29
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
IPC分类号： H01L29/40
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/324 , H01L21/823814 , H01L21/823835 , H01L29/4933
摘要： A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may significantly be improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.
摘要翻译：公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着提高单个半导体元件的器件性能或多个半导体元件的整体性能。此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。

7. 发明申请

US20050098818A1 Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers 审中-公开
标题翻译：包括掺杂的高k侧壁间隔物的场效应晶体管的漏极/源延伸结构
公开(公告)号：US20050098818A1
公开(公告)日：2005-05-12
申请号：US11015061
申请日：2004-12-17
申请人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek , Stephan Kruegel
发明人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek , Stephan Kruegel
IPC分类号： H01L21/225 , H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/2253 , H01L29/665 , H01L29/7833
摘要： High-k dielectric spacer elements on the gate electrode of a field effects transistor in combination with an extension region that is formed by dopant diffusion from the high-k spacer elements into the underlying semiconductor region provides for an increased charge carrier density in the extension region. In this way, the limitation of the charge carrier density to approximately the solid solubility of dopants in the extension region may be overcome, thereby allowing extremely shallow extension regions without unduly compromising the transistor performance.
摘要翻译：场效应晶体管的栅极上的高k电介质隔离元件与由高k隔离元件掺入到下面的半导体区域中的掺杂剂扩散形成的延伸区组合提供了延伸区中增加的电荷载流子密度。以这种方式，可以克服电荷载流子密度近似于扩散区域中掺杂剂的固溶度的限制，从而允许非常浅的延伸区域而不会不利地损害晶体管的性能。

8. 发明授权

US06838363B2 Circuit element having a metal silicide region thermally stabilized by a barrier diffusion material 有权
标题翻译：具有通过阻挡扩散材料热稳定的金属硅化物区域的电路元件
公开(公告)号：US06838363B2
公开(公告)日：2005-01-04
申请号：US10402585
申请日：2003-03-28
申请人： Karsten Wieczorek , Thorsten Kammler , Manfred Horstmann
发明人： Karsten Wieczorek , Thorsten Kammler , Manfred Horstmann
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/425
CPC分类号： H01L29/66507 , H01L21/26506 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6653
摘要： The introduction of a barrier diffusion material, such as nitrogen, into a silicon-containing conductive region, for example the drain and source regions and the gate electrode of a field effect transistor, allows the formation of nickel silicide, which is substantially thermally stable up to temperatures of 500° C. Thus, the device performance may significantly improve as the sheet resistance of nickel silicide is significantly less than that of nickel disilicide.
摘要翻译：诸如氮的阻挡扩散材料引入含硅导电区域，例如场效应晶体管的漏极和源极区域和栅电极，允许形成基本上热稳定的硅化镍到500℃的温度。因此，随着硅化镍的薄层电阻显着小于二硅化镍的薄膜电阻，器件性能可能显着提高。

9. 发明授权

US06806153B2 Method of manufacturing a field effect transistor 有权
标题翻译：制造场效应晶体管的方法
公开(公告)号：US06806153B2
公开(公告)日：2004-10-19
申请号：US10462893
申请日：2003-06-17
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2022 , H01L21/26506 , H01L21/26513
摘要： The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.
摘要翻译：本发明允许制造具有降低的热预算的场效应晶体管。第一非晶化区域和第二非晶区域通过注入非掺杂元素的离子形成在与栅电极相邻的衬底中，其不存在不会显着地改变衬底的导电性能。非晶化区域的形成可以在形成源极区域，漏极区域，扩展源极区域和延伸的漏极区域之前或之后进行。将衬底退火以实现非晶化区域的固相外延再生长并激活源极区域，漏极区域，扩展源极区域和延伸漏极区域中的掺杂剂。

10. 发明授权

US06798028B2 Field effect transistor with reduced gate delay and method of fabricating the same 有权
标题翻译：具有减小的栅极延迟的场效应晶体管及其制造方法
公开(公告)号：US06798028B2
公开(公告)日：2004-09-28
申请号：US09847622
申请日：2001-05-02
申请人： Manfred Horstmann , Rolf Stephan , Karsten Wieczorek , Stephan Kruegel
发明人： Manfred Horstmann , Rolf Stephan , Karsten Wieczorek , Stephan Kruegel
IPC分类号： H01L2976
CPC分类号： H01L21/28052 , H01L21/28114 , H01L29/42376 , H01L29/4933
摘要： A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.
摘要翻译：形成在基板上的晶体管包括栅电极，栅电极在栅极的脚处具有小于栅电极的平均横向延伸的横向延伸。与现有技术的器件的矩形横截面形状相比，栅电极的横截面增加提供了显着降低的栅极电阻，而有效栅极长度，即栅电极在其脚处的横向延伸可以是缩小到100nm以上的尺寸。此外，公开了一种用于形成上述场效应晶体管的方法。

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