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51. 发明授权

US07026679B2 Semiconductor integrated circuit device and the process of manufacturing the same having poly-silicon plug, wiring trenches and bit lines formed in the wiring trenches having a width finer than a predetermined size 有权
标题翻译：半导体集成电路器件及其制造方法，其具有形成在布线沟槽中的具有比预定尺寸更窄的宽度的多晶硅插塞，布线沟槽和位线
公开(公告)号：US07026679B2
公开(公告)日：2006-04-11
申请号：US10755393
申请日：2004-01-13
申请人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
发明人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/115 , H01L27/11526
摘要： A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
摘要翻译：通过使位线的宽度比由光刻的分辨率的极限决定的最小尺寸更窄，DRAM的存储单元的尺寸减小。通过在形成于氧化硅膜中的布线沟槽的内壁上形成氧化硅膜，并且在氧化硅膜内部形成位线，使位线变细。沉积形成在沟槽中的氧化硅膜，使得氧化硅膜具有比布线沟槽的宽度的一半更薄的厚度，并且在氧化硅膜内部的微细间隙中埋入金属膜作为位的材料线。

52. 发明申请

US20050186117A1 Gas detecting method and gas sensors 审中-公开
标题翻译：气体检测方法和气体传感器
公开(公告)号：US20050186117A1
公开(公告)日：2005-08-25
申请号：US10914271
申请日：2004-08-10
申请人： Hiroyuki Uchiyama , Kazuhiro Mochizuki , Akihisa Terano , Teruyuki Nakamura , Akihito Hongo , Tomoyoshi Kumagai
发明人： Hiroyuki Uchiyama , Kazuhiro Mochizuki , Akihisa Terano , Teruyuki Nakamura , Akihito Hongo , Tomoyoshi Kumagai
IPC分类号： G01N21/00 , G01N21/75 , G01N21/77 , G01N21/78
CPC分类号： G01N21/783 , G01N2021/7723 , G01N2021/7776 , G01N2021/7793
摘要： A gas detection method capable of solving the problem with respect to the operation at normal temperature that was impossible so far in the existent catalyst type sensor and detection with high sensitivity that was impossible by the light absorption type sensor. A multi-layered film formed of a first layer adsorbing a specified gas and a second layer having less adsorption are utilized as a detection film, and the detection film is disposed in the direction perpendicular to the optical channel and optically detects the change of stress caused in the detection film by gas adsorption as coupling loss. Alternatively, the stress generated in the detection film caused by gas adsorption is electrically detected by a piezoelectric element or capacitance element.
摘要翻译：一种气体检测方法，其能够解决在现有的催化剂型传感器中迄今为止不可能在常温下的操作的问题以及由光吸收型传感器不可能的高灵敏度的检测。使用由吸附特定气体的第一层形成的多层膜和具有较少吸附性的第二层形成的多层膜作为检测膜，并且将检测膜设置在与光学通道垂直的方向上，并且光学地检测所引起的应力变化在检测膜中通过气体吸附作为耦合损耗。或者，由压电元件或电容元件电气检测由气体吸附引起的检测膜中产生的应力。

53. 发明申请

US20050040497A1 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20050040497A1
公开(公告)日：2005-02-24
申请号：US10878358
申请日：2004-06-29
申请人： Chisaki Takubo , Hiroji Yamada , Kazuhiro Mochizuki , Kenichi Tanaka , Tomonori Tanoue , Hiroyuki Uchiyama
发明人： Chisaki Takubo , Hiroji Yamada , Kazuhiro Mochizuki , Kenichi Tanaka , Tomonori Tanoue , Hiroyuki Uchiyama
IPC分类号： H01L21/331 , H01L21/306 , H01L29/04 , H01L29/06 , H01L29/737
CPC分类号： H01L29/7371 , H01L21/30612 , H01L29/045 , H01L29/0657
摘要： The technical subject of the invention is to inhibit disconnection of electrodes caused by a step and bursting caused by residual air. That is, an object of the present invention is to provide a semiconductor device capable of overcoming a drawback due to the shape of a concave portion present in the zinc blende type compound semiconductor substrate in which the area of the bottom is larger than the surface in the cross sectional shape, as well as a manufacturing method thereof. According to the invention, a hole or step present in the semiconductor substrate constituting the semiconductor device is formed into a normal mesa shape irrespective of the orientation of the crystals on the surface of the semiconductor substrate. Accordingly, the present invention uses a novel wet etching solution having an etching rate for a portion below the etching mask higher than that in the direction of the depth of the semiconductor substrate.
摘要翻译：本发明的技术课题是抑制由残留空气引起的台阶和破裂引起的电极断开。也就是说，本发明的目的是提供一种半导体器件，其能够克服存在于闪锌矿型化合物半导体衬底中的凹部的形状的缺陷，其中底部的面积大于其中的表面横截面形状及其制造方法。根据本发明，构成半导体器件的半导体衬底中存在的孔或台阶形成为正常的台面形状，而与半导体衬底的表面上的晶体取向无关。因此，本发明使用对蚀刻掩模下方的蚀刻速度高于半导体衬底的深度方向的蚀刻速率的新型湿式蚀刻溶液。

54. 发明授权

US06407512B1 Flashing device of an automatic light-regulation type 有权
标题翻译：自动调光型闪光装置
公开(公告)号：US06407512B1
公开(公告)日：2002-06-18
申请号：US09710874
申请日：2000-11-14
申请人： Yutaka Yoshida , Takaaki Kotani , Katsumi Motomura , Wataru Sasaki , Yoshiaki Yamamoto , Hiroyuki Uchiyama
发明人： Yutaka Yoshida , Takaaki Kotani , Katsumi Motomura , Wataru Sasaki , Yoshiaki Yamamoto , Hiroyuki Uchiyama
IPC分类号： H05B3700
CPC分类号： H05B41/34 , G03B7/16 , G03B17/52 , G03B19/10
摘要： Flash light is repeatedly emitted in a pulse state by intermittently turning on and off an IGBT. The flash light reflected by a subject is received by a phototransistor to integrate a received light amount with a capacitor. While the IGBT is turned off, a charging voltage of the capacitor is converted to digital data. Based on the obtained data, it is judged whether emitting the flash light is stopped or not.
摘要翻译：通过间歇地导通和关断IGBT，闪光以脉冲状态重复发射。由被摄体反射的闪光被光电晶体管接收，以将接收的光量与电容器集成。当IGBT关断时，电容器的充电电压被转换为数字数据。基于获得的数据，判断是否停止闪光。

55. 发明授权

US06300237B1 Semiconductor integrated circuit device and method for making the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06300237B1
公开(公告)日：2001-10-09
申请号：US09245743
申请日：1999-02-08
申请人： Masayuki Suzuki , Shinji Nishihara , Masashi Sahara , Shinichi Ishida , Hiromi Abe , Sonoko Tohda , Hiroyuki Uchiyama , Hideaki Tsugane , Yoshiaki Yoshiura
发明人： Masayuki Suzuki , Shinji Nishihara , Masashi Sahara , Shinichi Ishida , Hiromi Abe , Sonoko Tohda , Hiroyuki Uchiyama , Hideaki Tsugane , Yoshiaki Yoshiura
IPC分类号： H01L214763
CPC分类号： H01L21/76862 , H01L21/32051 , H01L21/7684 , H01L21/76841 , H01L21/76843 , H01L21/76849 , H01L21/7685 , H01L23/53223 , H01L23/53266 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05083 , H01L2224/05124 , H01L2224/05166 , H01L2224/05184 , H01L2224/05187 , H01L2224/05624 , H01L2224/13099 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0104 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/01007 , H01L2924/04953 , H01L2924/00
摘要： A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminium film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
摘要翻译：一种制造半导体集成电路器件的方法包括以下步骤：（a）在具有多个通孔的绝缘膜上沉积由氮化钛制成的第一底层膜; （b）在第一底层膜上沉积钨膜，并通过含氟等离子体将钨膜回蚀刻，从而将钨膜留在连接孔中; （c）溅射蚀刻第一底层膜的表面以从第一底层膜的表面除去氟; 和（d）在第一底层膜上形成铝膜。还描述了通过该方法获得的半导体集成电路器件。

56. 发明授权

US6031288A Semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer and method of fabrication thereof 失效
标题翻译：用于通过钛硅化物层连接半导体区域和电布线金属的半导体集成电路器件及其制造方法
公开(公告)号：US6031288A
公开(公告)日：2000-02-29
申请号：US747392
申请日：1996-11-12
申请人： Hiromi Todorobaru , Hideo Miura , Masayuki Suzuki , Shinji Nishihara , Shuji Ikeda , Masashi Sahara , Shinichi Ishida , Hiromi Abe , Atushi Ogishima , Hiroyuki Uchiyama , Sonoko Abe
发明人： Hiromi Todorobaru , Hideo Miura , Masayuki Suzuki , Shinji Nishihara , Shuji Ikeda , Masashi Sahara , Shinichi Ishida , Hiromi Abe , Atushi Ogishima , Hiroyuki Uchiyama , Sonoko Abe
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L23/522 , H01L27/108 , H01L23/48
CPC分类号： H01L29/7845 , H01L23/485 , H01L23/5226 , H01L2924/0002
摘要： A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titanium silicide film formed in the contact holes. The thickness of the titanium silicide film is 10 nm to 120 nm or, preferably, 20 nm to 84 nm. Semiconductor regions and the electrical wiring metal are connected to each other through the titanium silicide film.
摘要翻译：半导体器件包括硅衬底，电布线金属，形成在硅衬底上的绝缘膜，形成在用于将硅衬底和电布线金属彼此连接的绝缘膜中的多个接触孔，以及硅化钛膜在接触孔中形成。硅化钛膜的厚度为10nm〜120nm，优选为20nm〜84nm。半导体区域和电布线金属通过硅化钛膜彼此连接。

57. 发明授权

US5904556A Method for making semiconductor integrated circuit device having interconnection structure using tungsten film 失效
标题翻译：制造具有使用钨膜的互连结构的半导体集成电路器件的方法
公开(公告)号：US5904556A
公开(公告)日：1999-05-18
申请号：US584065
申请日：1996-01-11
申请人： Masayuki Suzuki , Shinji Nishihara , Masashi Sahara , Shinichi Ishida , Hiromi Abe , Sonoko Tohda , Hiroyuki Uchiyama , Hideaki Tsugane , Yoshiaki Yoshiura
发明人： Masayuki Suzuki , Shinji Nishihara , Masashi Sahara , Shinichi Ishida , Hiromi Abe , Sonoko Tohda , Hiroyuki Uchiyama , Hideaki Tsugane , Yoshiaki Yoshiura
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76862 , H01L21/32051 , H01L21/7684 , H01L21/76841 , H01L21/76843 , H01L21/76849 , H01L21/7685 , H01L23/53223 , H01L23/53266 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05083 , H01L2224/05124 , H01L2224/05166 , H01L2224/05184 , H01L2224/05187 , H01L2224/05624 , H01L2224/13099 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L24/45 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/05042 , H01L2924/14
摘要： A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminium film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.
摘要翻译：一种制造半导体集成电路器件的方法包括以下步骤：（a）在具有多个通孔的绝缘膜上沉积由氮化钛制成的第一底层膜; （b）在第一底层膜上沉积钨膜，并通过含氟等离子体将钨膜回蚀刻，从而将钨膜留在连接孔中; （c）溅射蚀刻第一底层膜的表面以从第一底层膜的表面除去氟; 和（d）在第一底层膜上形成铝膜。还描述了通过该方法获得的半导体集成电路器件。

58. 发明授权

US5684315A Semiconductor memory device including memory cells each having an information storage capacitor component formed over control electrode of cell selecting transistor 失效
标题翻译：半导体存储器件包括存储单元，每个存储单元都具有形成在单元选择晶体管的控制电极上的信息存储电容器组件
公开(公告)号：US5684315A
公开(公告)日：1997-11-04
申请号：US362879
申请日：1994-12-23
申请人： Hiroyuki Uchiyama , Yoshiyuki Kaneko , Hiroki Soeda , Yasuhide Fujioka , Nozomu Matsuda , Motoko Sawamura
发明人： Hiroyuki Uchiyama , Yoshiyuki Kaneko , Hiroki Soeda , Yasuhide Fujioka , Nozomu Matsuda , Motoko Sawamura
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A semiconductor memory device has memory cells provided at intersections between word line conductors and data line conductors. Each of the memory cells includes a cell selecting transistor and an information storage capacitor. The capacitor in each of the memory cells includes a first capacitor component formed over the control electrode of the transistor and a second capacitor component formed over a word line conductor which is adjacent to a word line conductor integral with the control electrode of the transistor. Each of the first and second capacitor components has a common electrode, a storage electrode and a dielectric film sandwiched therebetween, and the storage electrode is at a level higher than the common electrode in each of said first and second capacitor components. The storage electrodes of the first and second capacitor components are electrically connected with each other and with one of the semiconductor regions of the transistor. The other semiconductor region of the transistor is electrically connected with one of the data line conductors. Patterning of the storage electrodes of the first and second capacitor components is preferalbly effected by use of masks of a stripe pattern.
摘要翻译：半导体存储器件具有在字线导体和数据线导体之间的交叉点处设置的存储单元。每个存储单元包括单元选择晶体管和信息存储电容器。每个存储单元中的电容器包括形成在晶体管的控制电极上的第一电容器部件和形成在字线导体上的第二电容器部件，该字线导体与与晶体管的控制电极成一体的字线导体相邻。第一电容器部件和第二电容器部件中的每一个均具有公共电极，存储电极和夹在其间的电介质膜，并且在所述第一和第二电容器部件的每个中，所述存储电极处于比所述公共电极高的电平。第一和第二电容器部件的存储电极彼此电连接并且与晶体管的半导体区域中的一个电连接。晶体管的另一个半导体区域与数据线导体之一电连接。第一和第二电容器部件的存储电极的图案化优选地通过使用条纹图案的掩模来实现。

59. 发明授权

US5426613A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
标题翻译：具有改进的基板布置以允许形成多种不同类型的随机存取存储器的半导体存储器件及其测试方法
公开(公告)号：US5426613A
公开(公告)日：1995-06-20
申请号：US972907
申请日：1992-11-06
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50 , G11C7/00 , G11C8/00
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
摘要翻译：提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。结合这些，接合垫被布置在适于不同包装类型的最佳位置处。还提供了各种布局布置以最小化空间并改善访问时间。提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

60. 发明授权

US5264712A Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same 失效
标题翻译：半导体集成电路及其制造方法及其制造装置
公开(公告)号：US5264712A
公开(公告)日：1993-11-23
申请号：US881314
申请日：1992-05-07
申请人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
发明人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
IPC分类号： H01L21/8234 , H01L27/105 , H01L21/308 , H01L29/66
CPC分类号： H01L27/105 , H01L21/823425
摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
摘要翻译：一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

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