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51. 发明授权

US08099621B2 Data reception apparatus and microcomputer having the same 有权
标题翻译：数据接收装置和具有该数据接收装置的微型计算机
公开(公告)号：US08099621B2
公开(公告)日：2012-01-17
申请号：US12285581
申请日：2008-10-09
申请人： Kazushi Matsuo , Toshihiko Matsuoka , Hideaki Ishihara
发明人： Kazushi Matsuo , Toshihiko Matsuoka , Hideaki Ishihara
IPC分类号： G06F1/04
CPC分类号： H03L1/025 , H03L1/026 , H03L7/06
摘要： A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value.
摘要翻译：数据接收装置包括：振荡电路，其根据周期设定值对来自CR振荡器的振荡信号进行倍数或分频，并输出与所述相乘或分频振荡信号对应的时钟信号; 温度检测器; 记忆时钟周期设定元件，其从存储器读取与温度对应的周期设定值，并将该周期设定值输入到振荡电路中; 接收器，接收由时钟信号定义的数据信号; 测量元件，通过对时钟信号进行计数来测量数据信号的单位比特长度; 以及校正元件，其基于时钟信号的计数值和与单位比特长度对应的基准周期的基准计数值来校正周期设定值，并且以修正的周期设定值重写周期设定值。

52. 发明授权

US07810659B2 Boom component display apparatus 有权
标题翻译：动臂部件显示装置
公开(公告)号：US07810659B2
公开(公告)日：2010-10-12
申请号：US12329046
申请日：2008-12-05
申请人： Hideaki Ishihara
发明人： Hideaki Ishihara
IPC分类号： B66C23/70
CPC分类号： B66C23/70 , B66C23/905
摘要： A boom component display apparatus 1 of the present invention is provided with processing units 4, connector assemblies 6 and a display unit 5. The processing units 4 are installed on each of a plurality of unit booms 11a thru 11g that compose a boom assembly 3 of a crane 100 and outputs identification information of each unit boom. The connector assemblies 6 transmits the identification information outputted from the processing units 4. The display unit 5 displays a connecting sequence information to show the relation between the connecting sequence of a plurality of unit booms 11a thru 11g and the identification information of a plurality of unit booms 11a thru 11g, basing on the identification information sent from the processing units 4 through the connector assemblies 6. By depending upon the boom component display apparatus of the present invention, it is possible to prevent the unit booms from being assembled in the wrong connecting sequences.
摘要翻译：本发明的起重臂部件显示装置1设有处理单元4，连接器组件6和显示单元5.处理单元4安装在构成起重臂组件3的多个单元臂11a至11g中的每一个上起重机100，并且输出每个单元起重臂的识别信息。连接器组件6发送从处理单元4输出的识别信息。显示单元5显示连接序列信息以显示多个单元吊杆11a至11g的连接顺序与多个单元的识别信息之间的关系悬臂11a至11g，基于从处理单元4通过连接器组件6发送的识别信息。根据本发明的悬臂部件显示装置，可以防止单元悬臂组装在错误的连接序列。

53. 发明授权

US07725694B2 Processor, microcomputer and method for controlling program of microcomputer 有权
标题翻译：微机控制程序的处理器，微机及方法
公开(公告)号：US07725694B2
公开(公告)日：2010-05-25
申请号：US11312830
申请日：2005-12-21
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Akimasa Niwa , Takayuki Matsuda , Toshihiko Matsuoka
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3842 , G06F9/3861
摘要： A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgment instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgment instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgment instruction.
摘要翻译：微型计算机包括能够在并行分时操作中执行多个任务的CPU。这些任务包括至少一个具有固定循环程序的特殊任务，其具有指令地址的不断增加。当CPU在特殊任务中执行条件判断指令时，CPU在不需要执行特殊操作中描述的指令的情况下禁止将CPU和外围电路两者的条件判断指令的执行结果反映条件判决指示后的任务。

54. 发明申请

US20100017641A1 Communication system communication device and method for determining duty ratio of PWM control 有权
标题翻译：通信系统通信装置及确定PWM控制占空比的方法
公开(公告)号：US20100017641A1
公开(公告)日：2010-01-21
申请号：US12585673
申请日：2009-09-22
申请人： Katsutoyo Misawa , Masato Rinnai , Toshihiko Matsuoka , Hideaki Ishihara
发明人： Katsutoyo Misawa , Masato Rinnai , Toshihiko Matsuoka , Hideaki Ishihara
IPC分类号： G06F1/06
CPC分类号： H04L12/403 , H04L12/10 , H04L12/40045 , H04L12/66 , H04L2012/40273
摘要： A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.
摘要翻译：通信系统包括：主人; 多个奴隶; 以及用于在主机和多个从机之间耦合的总线，以便在主机和多个从机之间异步通信。主人在供电期间为公共汽车供电。主器件或从器件在数据传输周期内通过总线驱动总线以发送一位数据。连续执行电源周期和数据传输周期，使得在主机和多个从机之间执行由多个一比特周期提供的数据通信。主人精细地改变数据通信中的通信频率。主机将数据通信中总线的驱动级别改变在预定的可接受范围内。

55. 发明授权

US07560996B2 Frequency-multiplied clock signal output circuit 失效
标题翻译：倍频时钟信号输出电路
公开(公告)号：US07560996B2
公开(公告)日：2009-07-14
申请号：US11882131
申请日：2007-07-31
申请人： Yasuyuki Ishikawa , Yoshinori Teshima , Hideaki Ishihara
发明人： Yasuyuki Ishikawa , Yoshinori Teshima , Hideaki Ishihara
IPC分类号： H03L7/181
CPC分类号： H03L7/0995 , H03L7/18
摘要： In a DPLL circuit, when the size of a data value which is output from a data latch circuit and should be naturally set in a 11-bit down-counter becomes equal to or more than 12 bits, an overflow preventing circuit substitutes the 11-bit data for the data value.
摘要翻译：在DPLL电路中，当从数据锁存电路输出并且应当自然地设置在11位递减计数器中的数据值的大小变为等于或大于12位时，溢出防止电路将11- 数据值的位数据。

56. 发明申请

US20080140920A1 Microcomputer for flash memory rewriting 有权
标题翻译：微机用于闪存重写
公开(公告)号：US20080140920A1
公开(公告)日：2008-06-12
申请号：US12000001
申请日：2007-12-06
申请人： Masahiro Kamiya , Kyouichi Suzuki , Naoki Itoh , Hideaki Ishihara
发明人： Masahiro Kamiya , Kyouichi Suzuki , Naoki Itoh , Hideaki Ishihara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： A microcomputer and method are provided capable of restarting a rewrite program without the need for changing a mode using an external terminal when rewriting nonvolatile memory fails. A CPU of a microcomputer executes a rewrite program to clear FLASH status 0 of flash memory and rewrite all areas in it. The CPU finally writes a rewrite completion code to FLASH status 0. The CPU executes a determination program to read FLASH status 0 of the flash memory. The CPU reads ID status information when read data does not match the rewrite completion code. The CPU re-executes the rewrite program when the data matches ID status information.
摘要翻译：提供一种微计算机和方法，其能够在重写非易失性存储器失败时重新启动重写程序，而不需要使用外部端子改变模式。微型计算机的CPU执行重写程序来清除闪存的FLASH状态0并重写其中的所有区域。 CPU最终将重写完成代码写入FLASH状态0。 CPU执行确定程序以读取闪存的FLASH状态0。当读取数据与重写完成代码不匹配时，CPU读取ID状态信息。当数据与ID状态信息匹配时，CPU重新执行重写程序。

57. 发明申请

US20080104370A1 RISC type of CPU and compiler to produce object program executed by the same 审中-公开
标题翻译： RISC类型的CPU和编译器来产生由其执行的对象程序
公开(公告)号：US20080104370A1
公开(公告)日：2008-05-01
申请号：US11998966
申请日：2007-12-03
申请人： Masahiro Kamiya , Yoshinori Teshima , Hideaki Ishihara
发明人： Masahiro Kamiya , Yoshinori Teshima , Hideaki Ishihara
IPC分类号： G06F9/30
CPC分类号： G06F9/4812 , G06F8/447 , G06F9/30054 , G06F9/3842 , G06F9/3877 , G06F9/4486
摘要： A RISC type of CPU is provided to execute an object program in which a stack area is used. The CPU is configured to have a return instruction based on an operand at which an open size is specified and to perform the return instruction when the stack area is required to be opened in returning processing executed by the CPU from interrupt processing to ordinary processing with no interrupt. Also a compiler is provided to compile a source program into the object program. The compiler determines whether or not a stack area in the source program is required to be opened when processing in the source program is returned from interrupt processing to ordinary processing with no interrupt and produces codes of the object program in which an operand for a return instruction is included and an open size for the stack area is specified at the operand.
摘要翻译：提供RISC类型的CPU来执行其中使用堆栈区域的对象程序。 CPU被配置为具有基于指定了开放大小的操作数的返回指令，并且当在CPU执行的返回处理中需要打开堆栈区域时，执行返回指令，从中断处理到无处理的普通处理打断。还提供了一个编译器来将源程序编译到对象程序中。编译器确定源程序中的堆栈区是否需要打开，源程序中的处理从中断处理返回到无中断的普通处理，并产生其中用于返回指令的操作数的对象程序的代码并且在操作数中指定了堆栈区域的开放大小。

58. 发明申请

US20080084250A1 Frequency-multiplied clock signal output circuit 失效
标题翻译：倍频时钟信号输出电路
公开(公告)号：US20080084250A1
公开(公告)日：2008-04-10
申请号：US11882131
申请日：2007-07-31
申请人： Yasuyuki Ishikawa , Yoshinori Teshima , Hideaki Ishihara
发明人： Yasuyuki Ishikawa , Yoshinori Teshima , Hideaki Ishihara
IPC分类号： H03L7/099 , H03K3/03
CPC分类号： H03L7/0995 , H03L7/18
摘要： In a DPLL circuit, when the size of a data value which is output from a data latch circuit and should be naturally set in a 11-bit down-counter becomes equal to or more than 12 bits, an overflow preventing circuit substitutes the 11-bit data for the data value.
摘要翻译：在DPLL电路中，当从数据锁存电路输出并且应当自然地设置在11位递减计数器中的数据值的大小变为等于或大于12位时，溢出防止电路将11- 数据值的位数据。

59. 发明授权

US07149915B2 Microcomputer using a shared counter 有权
标题翻译：微电脑使用共享计数器
公开(公告)号：US07149915B2
公开(公告)日：2006-12-12
申请号：US10784252
申请日：2004-02-24
申请人： Toshihiko Matsuoka , Yukari Ishiguro , Hideaki Ishihara
发明人： Toshihiko Matsuoka , Yukari Ishiguro , Hideaki Ishihara
IPC分类号： G06F1/14
CPC分类号： G06F11/0757
摘要： In a microcomputer, a watch-dog timer and a sleep control timer share a counter in their signal generating circuits. In a normal operation mode, an AND gate is in a signal passing state and a reset signal RST can be outputted. In a sleep mode, another AND gate is in a signal passing state and a wake-up signal WKUP can be outputted.
摘要翻译：在微计算机中，看门狗定时器和睡眠控制定时器在其信号发生电路中共享计数器。在正常操作模式中，与门处于信号通过状态，并且可以输出复位信号RST。在休眠模式中，另一个与门处于信号通过状态，并且可以输出唤醒信号WKUP。

60. 发明申请

US20050033998A1 Power supply circuit and semiconductor integrated circuit device 审中-公开
标题翻译：电源电路和半导体集成电路器件
公开(公告)号：US20050033998A1
公开(公告)日：2005-02-10
申请号：US10911743
申请日：2004-08-05
申请人： Yoshimitsu Honda , Yoshinori Teshima , Hideaki Ishihara , Toshihiko Matsuoka , Katsutoyo Misawa
发明人： Yoshimitsu Honda , Yoshinori Teshima , Hideaki Ishihara , Toshihiko Matsuoka , Katsutoyo Misawa
IPC分类号： G05F1/10 , G05F1/56 , G06F1/26 , G06F1/32 , G06F1/30
CPC分类号： G06F1/3228 , G06F1/26
摘要： In a power supply circuit, when switches are turned off, current flows from a battery power supply line through resistors, input terminals, diodes and a terminal and further from a terminal into IC. When a microcomputer operates in a low power consumption operating mode, the power supply voltage is higher than a target voltage, and a control voltage output from an operational amplifier increases, so that a transistor is turned off. At this time, a current sink circuit operates and a transistor is turned on, so that excessive current flows into the current sink circuit to suppress increase of the power supply voltage.
摘要翻译：在电源电路中，当开关断开时，电流从电池电源线通过电阻器，输入端子，二极管和端子进一步从端子流入IC。当微型计算机在低功耗操作模式下工作时，电源电压高于目标电压，并且从运算放大器输出的控制电压增加，从而关断晶体管。此时，电流吸收电路工作并且晶体管导通，使得过大的电流流入电流吸收电路以抑制电源电压的增加。

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