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1. 发明授权

US07634547B2 Communication network system, and ID allocating method and ID setting method for communication network system 有权
标题翻译：通信网络系统，通信网络系统的ID分配方法和ID设置方法
公开(公告)号：US07634547B2
公开(公告)日：2009-12-15
申请号：US11004971
申请日：2004-12-07
申请人： Yukari Ishiguro , Hideaki Ishihara , Toshihiko Matsuoka
发明人： Yukari Ishiguro , Hideaki Ishihara , Toshihiko Matsuoka
IPC分类号： G06F15/16 , G06F15/177
CPC分类号： H04L61/2038 , H04L29/12254
摘要： When each slave ECU is powered on and activated while connected to a communication network through a harness, it reads out divided voltage potential applied by voltage dividing resistors in each ID determining signal line, and allows reception of a data packet transmitted from control ECU when a wait time corresponding to the divided voltage potential elapses. The control ECU successively transmits a data packet containing as a main body ID data to be allocated to each slave ECU, and each slave ECU sets ID data transmitted as its own ID.
摘要翻译：当每个从ECU在通过线束连接到通信网络时通电并激活时，它读出每个ID确定信号线中的分压电阻施加的分压电压，并允许接收从控制ECU发送的数据分组等待时间对应于分压后的电压电位。控制ECU依次发送包含要分配给每个从ECU的主体ID数据的数据分组，并且每个从ECU设置作为其自身ID发送的ID数据。

2. 发明申请

US20050152388A1 Communication network system, and ID allocating method and ID setting method for communication network system 有权
标题翻译：通信网络系统，通信网络系统的ID分配方法和ID设置方法
公开(公告)号：US20050152388A1
公开(公告)日：2005-07-14
申请号：US11004971
申请日：2004-12-07
申请人： Yukari Ishiguro , Hideaki Ishihara , Toshihiko Matsuoka
发明人： Yukari Ishiguro , Hideaki Ishihara , Toshihiko Matsuoka
IPC分类号： H04L12/28 , H04L29/12
CPC分类号： H04L61/2038 , H04L29/12254
摘要： When each slave ECU is powered on and activated while connected to a communication network through a harness, it reads out divided voltage potential applied by voltage dividing resistors in each ID determining signal line, and allows reception of a data packet transmitted from control ECU when a wait time corresponding to the divided voltage potential elapses. The control ECU successively transmits a data packet containing as a main body ID data to be allocated to each slave ECU, and each slave ECU sets ID data transmitted as its own ID.
摘要翻译：当每个从ECU在通过线束连接到通信网络时通电并激活时，它读出每个ID确定信号线中的分压电阻施加的分压电压，并允许接收从控制ECU发送的数据分组等待时间对应于分压后的电压电位。控制ECU依次发送包含要分配给每个从ECU的主体ID数据的数据分组，并且每个从ECU设置作为其自身ID发送的ID数据。

3. 发明授权

US07149915B2 Microcomputer using a shared counter 有权
标题翻译：微电脑使用共享计数器
公开(公告)号：US07149915B2
公开(公告)日：2006-12-12
申请号：US10784252
申请日：2004-02-24
申请人： Toshihiko Matsuoka , Yukari Ishiguro , Hideaki Ishihara
发明人： Toshihiko Matsuoka , Yukari Ishiguro , Hideaki Ishihara
IPC分类号： G06F1/14
CPC分类号： G06F11/0757
摘要： In a microcomputer, a watch-dog timer and a sleep control timer share a counter in their signal generating circuits. In a normal operation mode, an AND gate is in a signal passing state and a reset signal RST can be outputted. In a sleep mode, another AND gate is in a signal passing state and a wake-up signal WKUP can be outputted.
摘要翻译：在微计算机中，看门狗定时器和睡眠控制定时器在其信号发生电路中共享计数器。在正常操作模式中，与门处于信号通过状态，并且可以输出复位信号RST。在休眠模式中，另一个与门处于信号通过状态，并且可以输出唤醒信号WKUP。

4. 发明申请

US20090009211A1 Microcomputer and functional evaluation chip 有权
标题翻译：微电脑和功能评估芯片
公开(公告)号：US20090009211A1
公开(公告)日：2009-01-08
申请号：US12155017
申请日：2008-05-29
申请人： Naoki Ito , Hideaki Ishihara , Toshihiko Matsuoka , Katsutoyo Misawa
发明人： Naoki Ito , Hideaki Ishihara , Toshihiko Matsuoka , Katsutoyo Misawa
IPC分类号： H03K19/00
CPC分类号： G06F11/26
摘要： A microcomputer for functioning according to operation modes includes: a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.
摘要翻译：根据操作模式起作用的微计算机包括：对施加到模式设置终端的信号中的电平变化次数进行计数的模式计数器; 解码模式计数器的输出数据以输出表示一种操作模式的模式信号的模式解码器; 时钟输入端子; 数据终端，串行数据与施加到时钟输入端的串行时钟信号同步输入; 串行到并行转换单元，将串行数据转换为并行数据，并将并行数据存储在输入数据缓冲器中; 以及切换装置，切换到CPU能够以测试模式访问输入数据缓冲器的状态。在测试模式下，能够从外部电路输入测试指令数据。

5. 发明授权

US07444529B2 Microcomputer having rewritable nonvolatile memory 失效
标题翻译：微计算机具有可重写的非易失性存储器
公开(公告)号：US07444529B2
公开(公告)日：2008-10-28
申请号：US11238106
申请日：2005-09-29
申请人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
发明人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
IPC分类号： G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/128
摘要： A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the circuits or interrupts or resumes the supply of an external power source in response to resumption of the halted operation. When the CPU is to be shifted to the sleep mode, the frequency multiplier circuit holds the set oscillation control conditions. When the oscillating operation is to be resumed, operates based on the oscillation control conditions that are held. When the sleep mode is reset, the CPU makes access to the mask ROM and immediately reads out a control program that is to be executed right after the wakeup.
摘要翻译： CPU在转移到休眠模式时，通过低功耗控制电路中止振荡电路和倍频器电路的振荡操作。闪光电源电路中断电路或中断的振荡操作或响应于恢复停止的操作来恢复外部电源的供应。当CPU被切换到睡眠模式时，倍频电路保持设定的振荡控制条件。当振荡操作要恢复时，基于所保持的振荡控制条件进行操作。当睡眠模式复位时，CPU访问掩码ROM，并立即读出在唤醒之后要执行的控制程序。

6. 发明申请

US20060069933A1 Microcomputer having rewritable nonvolatile memory 失效
标题翻译：微计算机具有可重写的非易失性存储器
公开(公告)号：US20060069933A1
公开(公告)日：2006-03-30
申请号：US11238106
申请日：2005-09-29
申请人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
发明人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
IPC分类号： G06F1/26
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/128
摘要： A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the circuits or interrupts or resumes the supply of an external power source in response to resumption of the halted operation. When the CPU is to be shifted to the sleep mode, the frequency multiplier circuit holds the set oscillation control conditions. When the oscillating operation is to be resumed, operates based on the oscillation control conditions that are held. When the sleep mode is reset, the CPU makes access to the mask ROM and immediately reads out a control program that is to be executed right after the wakeup.
摘要翻译： CPU在转移到休眠模式时，通过低功耗控制电路中止振荡电路和倍频器电路的振荡操作。闪光电源电路中断电路或中断的振荡操作或响应于恢复停止的操作来恢复外部电源的供应。当CPU被切换到睡眠模式时，倍频电路保持设定的振荡控制条件。当振荡操作要恢复时，基于所保持的振荡控制条件进行操作。当睡眠模式复位时，CPU访问掩码ROM，并立即读出在唤醒之后要执行的控制程序。

7. 发明授权

US07554415B2 Microcomputer including a CR oscillator circuit 有权
标题翻译：微电脑包括CR振荡电路
公开(公告)号：US07554415B2
公开(公告)日：2009-06-30
申请号：US11640876
申请日：2006-12-19
申请人： Toshihiko Matsuoka , Hideaki Ishihara
发明人： Toshihiko Matsuoka , Hideaki Ishihara
IPC分类号： H03B5/24 , H03K3/02 , H03L1/02 , H03L7/06
CPC分类号： H03L1/026 , H03L1/027 , H03L7/0996 , H03L7/16
摘要： A microcomputer includes an oscillator for generating a clock signal having a frequency by using a CR circuit, a multiplier for outputting the clock signal having a multiplied frequency relative to the frequency generated by the oscillator based on data from an external source, a temperature detection unit for detecting temperature at a proximity of the CR circuit, a storage unit for storing data that enables the multiplied frequency of the clock signal in an output from the multiplier to have a constant value based on a temperature-dependent oscillation characteristic of the oscillator, and a control unit for setting a multiplication value for generating the multiplied frequency of the clock signal to the multiplier based on the data in the storage unit that is correlated to the temperature detected by the temperature detection unit.
摘要翻译：微型计算机包括用于通过使用CR电路产生具有频率的时钟信号的振荡器，用于根据来自外部源的数据输出相对于由振荡器产生的频率具有相乘频率的时钟信号的乘法器，温度检测单元用于检测所述CR电路附近的温度，存储单元，用于存储使所述乘法器的输出中的时钟信号的倍频能够基于所述振荡器的温度相关振荡特性而具有恒定值的数据;以及控制单元，用于根据与由温度检测单元检测到的温度相关的存储单元中的数据，将用于产生时钟信号的倍频的乘法值设置到乘法器。

8. 发明授权

US07982512B2 Communication system communication device and method for determining duty ratio of PWM control 有权
标题翻译：通信系统通信装置及确定PWM控制占空比的方法
公开(公告)号：US07982512B2
公开(公告)日：2011-07-19
申请号：US12585673
申请日：2009-09-22
申请人： Katsutoyo Misawa , Masato Rinnai , Toshihiko Matsuoka , Hideaki Ishihara
发明人： Katsutoyo Misawa , Masato Rinnai , Toshihiko Matsuoka , Hideaki Ishihara
IPC分类号： H03K3/017
CPC分类号： H04L12/403 , H04L12/10 , H04L12/40045 , H04L12/66 , H04L2012/40273
摘要： A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.
摘要翻译：通信系统包括：主人; 多个奴隶; 以及用于在主机和多个从机之间耦合的总线，以便在主机和多个从机之间异步通信。主人在供电期间向公共汽车供电。主器件或从器件在数据传输周期内通过总线驱动总线以发送一位数据。连续执行电源周期和数据传输周期，使得在主机和多个从机之间执行由多个一比特周期提供的数据通信。主人精细地改变数据通信中的通信频率。主机将数据通信中总线的驱动级别改变在预定的可接受范围内。

9. 发明申请

US20090096504A1 Data reception apparatus and microcomputer having the same 有权
标题翻译：数据接收装置和具有该数据接收装置的微型计算机
公开(公告)号：US20090096504A1
公开(公告)日：2009-04-16
申请号：US12285581
申请日：2008-10-09
申请人： Kazushi Matsuo , Toshihiko Matsuoka , Hideaki Ishihara
发明人： Kazushi Matsuo , Toshihiko Matsuoka , Hideaki Ishihara
IPC分类号： H03K3/011
CPC分类号： H03L1/025 , H03L1/026 , H03L7/06
摘要： A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value.
摘要翻译：数据接收装置包括：振荡电路，其根据周期设定值对来自CR振荡器的振荡信号进行倍数或分频，并输出与所乘的或分频的振荡信号对应的时钟信号; 温度检测器; 记忆时钟周期设定元件，其从存储器读取与温度对应的周期设定值，并将该周期设定值输入到振荡电路中; 接收器，接收由时钟信号定义的数据信号; 测量元件，通过对时钟信号进行计数来测量数据信号的单位比特长度; 以及校正元件，其基于时钟信号的计数值和与单位比特长度对应的基准周期的基准计数值来校正周期设定值，并且以修正的周期设定值重写周期设定值。

10. 发明授权

US07467294B2 Microcomputer with mode decoder operable upon receipt of either power-on or external reset signal 有权
标题翻译：具有模式解码器的微计算机，在接收到电源接通或外部复位信号时可操作
公开(公告)号：US07467294B2
公开(公告)日：2008-12-16
申请号：US11270447
申请日：2005-11-10
申请人： Toshihiko Matsuoka , Naoki Ito , Hideaki Ishihara , Yasuyuki Ishikawa
发明人： Toshihiko Matsuoka , Naoki Ito , Hideaki Ishihara , Yasuyuki Ishikawa
IPC分类号： G06F9/00
CPC分类号： G06F1/24
摘要： A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.
摘要翻译：微型计算机包括多个操作模式选择端子，用于选择多个操作模式的数据。多个操作模式选择端子被设计为可用作通用输入端子或输出端子。解码器将对多个操作模式选择端子设置的数据进行解码，并根据选择的操作模式输出用于切换内部功能的模式信号。定时信号输出单元向解码器输出用于使解码器执行解码操作的定时信号。当上电复位和外部控制的复位中的至少一个从活动状态变为非活动状态时，定时信号输出单元输出定时信号。

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