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51. 发明申请

US20070241768A1 CHANGING CHIP FUNCTION BASED ON FUSE STATES 有权
标题翻译：基于保险丝状态改变芯片功能
公开(公告)号：US20070241768A1
公开(公告)日：2007-10-18
申请号：US11760575
申请日：2007-06-08
申请人： KARL ERICKSON , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： KARL ERICKSON , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： G11C8/20
CPC分类号： G06F21/71
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。操作和/或访问可以基于存储在诸如电可编程熔丝（eFUSES）的非易失性存储元件中的值来提供。

52. 发明申请

US20070018280A1 Antifuse structure and system for closing thereof 失效
标题翻译：防腐结构及其闭合系统
公开(公告)号：US20070018280A1
公开(公告)日：2007-01-25
申请号：US11527343
申请日：2006-09-26
申请人： William Motsiff , William Tonti , Richard Williams
发明人： William Motsiff , William Tonti , Richard Williams
IPC分类号： H01L29/00 , H01L21/326
CPC分类号： H01L23/5252 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.
摘要翻译：一种用于提供通过静电辅助由激光能量闭合的反熔丝的结构和方法。在半导体结构之间形成两个或更多个金属段，在金属段之间具有气隙或多孔电介质。将脉冲激光能量施加到一个或多个金属片段，同时在金属片段之间施加电压电位以产生静电场。脉冲激光能量软化金属片段，静电场使金属片段彼此接触。静电场减少必须施加到半导体结构以关闭反熔丝的激光能量的量。

53. 发明申请

US20060289864A1 High impedance antifuse 有权
公开(公告)号：US20060289864A1
公开(公告)日：2006-12-28
申请号：US11482688
申请日：2006-07-07
申请人： John Fifield , Russell Houghton , William Tonti
发明人： John Fifield , Russell Houghton , William Tonti
IPC分类号： H01L29/04 , H01L29/74 , H01L29/76 , H01L29/00 , H01L23/62
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.

54. 发明申请

US20060220174A1 E-Fuse and anti-E-Fuse device structures and methods 审中-公开
标题翻译：电子熔断器和反电子保险丝器件的结构和方法
公开(公告)号：US20060220174A1
公开(公告)日：2006-10-05
申请号：US11440199
申请日：2006-05-24
申请人： Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
发明人： Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Standard photolithography is used to pattern and fabricate a final polysilicon wafer imaged structure which is smaller than normal allowable photo-lithographic minimum dimensions. Three different methods are provided to produce such sub-minimum dimension structures, a first method uses a photolithographic mask with a sub-minimum space between minimum size pattern features of the mask, a second method uses a photolithographic mask with a sub-minimum widthwise jog or offset between minimum size pattern features of the mask, and a third method is a combination of the first and second methods. Each of the three methods can be used with three different embodiments, a first embodiment is a polysilicon E-Fuse with a sub-minimum width polysilicon fuse line, a second embodiment is a work function altered/programmed self-aligned MOSFET E-Fuse with a sub-minimum width fuse line, and a third embodiment is a polysilicon MOSFET E-Fuse with a sub-minimum width fuse line which is programmed with a low trigger voltage snapback.
摘要翻译：使用标准光刻法来图案化和制造最终的多晶硅晶片成像结构，该结构小于正常允许光刻最小尺寸。提供了三种不同的方法来产生这样的次最小维度结构，第一种方法使用具有掩模的最小尺寸图案特征之间的亚最小空间的光刻掩模，第二种方法使用光刻掩模与次最小宽度方向点动或掩模的最小尺寸图案特征之间的偏移，第三种方法是第一和第二方法的组合。三种方法中的每一种可以与三种不同的实施例一起使用，第一实施例是具有亚最小宽度多晶硅熔丝线的多晶硅E熔丝，第二实施例是工作功能改变/编程的自对准MOSFET E-Fuse，具有亚最小宽度熔丝线，第三实施例是具有低电平触发电压快速编程的亚最小宽度熔丝线的多晶硅MOSFET E-Fuse。

55. 发明申请

US20060136751A1 Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable 有权
公开(公告)号：US20060136751A1
公开(公告)日：2006-06-22
申请号：US11016219
申请日：2004-12-17
申请人： Anthony Bonaccio , Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Anthony Bonaccio , Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： G06F12/14
CPC分类号： G06F12/1433 , G06F21/6245
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

56. 发明申请

US20050287718A1 INTEGRATED SOI FINGERED DECOUPLING CAPACITOR 有权
标题翻译：集成的SOI手指解除电容器
公开(公告)号：US20050287718A1
公开(公告)日：2005-12-29
申请号：US10710256
申请日：2004-06-29
申请人： Zachary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
发明人： Zachary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
IPC分类号： H01L21/00 , H01L21/334 , H01L21/336 , H01L21/8242 , H01L21/84 , H01L27/06 , H01L27/08 , H01L27/12
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/0629 , H01L27/0805 , H01L27/1087 , H01L27/1203
摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.
摘要翻译：本发明提供了一种在本体硅区域中的指状去耦电容器，其通过在本体硅区域中蚀刻一系列最小或次最小沟槽而形成，氧化这些沟槽，从至少一个或多个不相交的沟槽中去除氧化物，具有原位掺杂多晶硅的沟槽，后来通过离子注入掺杂的本征多晶硅，或者用金属柱（例如钨）填充并形成标准互连到电容器板。

57. 发明申请

US20050199907A1 STRUCTURE AND METHOD OF FORMING A BIPOLAR TRANSISTOR HAVING A VOID BETWEEN EMITTER AND EXTRINSIC BASE 失效
标题翻译：形成具有发射极和极端基底之间的空穴的双极晶体管的结构和方法
公开(公告)号：US20050199907A1
公开(公告)日：2005-09-15
申请号：US10708563
申请日：2004-03-11
申请人： Rama Divakaruni , Gregory Freeman , Marwan Khater , William Tonti
发明人： Rama Divakaruni , Gregory Freeman , Marwan Khater , William Tonti
IPC分类号： H01L21/331 , H01L27/06 , H01L27/082 , H01L29/06 , H01L29/737 , H01L31/072
CPC分类号： H01L29/66242 , H01L27/0623 , H01L29/0649 , H01L29/7378
摘要： Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap and a vacuum void.
摘要翻译：提供了用于制造双极晶体管的结构和方法，双极晶体管包括集电极，覆盖集电极的本征基极，覆盖本征基极的发射极以及与发射极间隔开的非本征基极，该间隙至少包括一个气隙和一个真空空隙。

58. 发明申请

US20050186744A1 MOSFET with decoupled halo before extension 失效
标题翻译：扩展前分离光环的MOSFET
公开(公告)号：US20050186744A1
公开(公告)日：2005-08-25
申请号：US10785895
申请日：2004-02-24
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier, , Carl Radens , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier, , Carl Radens , William Tonti
IPC分类号： H01L21/28 , H01L21/336 , H01L21/425 , H01L21/8234 , H01L29/423
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/42376 , H01L29/66553 , H01L29/6659
摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.
摘要翻译：反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响旨在改变装置的串联电阻。逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

59. 发明申请

US20050073023A1 ELECTRONICALLY PROGRAMMABLE ANTIFUSE AND CIRCUITS MADE THEREWITH 失效
标题翻译：电子可编程抗体和电路
公开(公告)号：US20050073023A1
公开(公告)日：2005-04-07
申请号：US10605523
申请日：2003-10-06
申请人： John Fifield , Wagdi Abadeer , William Tonti
发明人： John Fifield , Wagdi Abadeer , William Tonti
IPC分类号： H01L23/525 , H01L21/82 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

60. 发明授权

US06528855B2 MOSFET having a low aspect ratio between the gate and the source/drain 失效
标题翻译： MOSFET在栅极和源极/漏极之间具有低的纵横比
公开(公告)号：US06528855B2
公开(公告)日：2003-03-04
申请号：US09911894
申请日：2001-07-24
申请人： Qiuyi Ye , William Tonti , Yujun Li , Jack A. Mandelman
发明人： Qiuyi Ye , William Tonti , Yujun Li , Jack A. Mandelman
IPC分类号： H01L29772
CPC分类号： H01L29/0653 , H01L21/823814 , H01L21/823878 , H01L29/66621 , H01L29/66636 , H01L29/7834
摘要： A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.
摘要翻译：具有新的源极/漏极（S / D）结构的MOSFET特别适用于现代CMOS技术的较小特征尺寸。 S / D导体位于浅沟槽隔离（STI）上，以实现低结漏电和低结电容。通过STI蚀刻步骤（根据制造MOSFET的第一种方法）或硅蚀刻步骤（根据制造MOSFET的第二种方法）限定S / D结深度。通过控制蚀刻深度，实现非常浅的结深度。栅极长度的变化很小，因为栅极区域是通过蚀刻晶体硅来定义的，而不是蚀刻多晶硅。由于栅极导体和源极和漏极导体在同一个电平上对齐，栅极和S / D之间的纵横比较低。自杀技术应用于源极和漏极，用于低寄生电阻; 然而，这不会导致严重的S / D结泄漏，因为源极和漏极导体位于STI上。

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