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51. 发明授权

US07642588B2 Memory cells with planar FETs and vertical FETs with a region only in upper region of a trench and methods of making and using same 有权
标题翻译：具有平面FET的存储单元和仅在沟槽的上部区域中的区域的垂直FET，以及制造和使用它们的方法
公开(公告)号：US07642588B2
公开(公告)日：2010-01-05
申请号：US11259296
申请日：2005-10-26
申请人： Kangguo Cheng , Jack A. Mandelman
发明人： Kangguo Cheng , Jack A. Mandelman
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , G11C11/403 , G11C11/405 , H01L27/0207 , H01L27/10864 , H01L27/10894 , H01L29/045
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory cell of a substrate that includes (1) a PFET with an orientation approximately planar to a surface of the substrate; and (2) an NFET coupled to the approximately planar PFET. An orientation of the NFET in the substrate is approximately perpendicular to the orientation of the PFET. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是基板的存储单元，其包括（1）具有与基板的表面近似平面的取向的PFET; 和（2）耦合到大致平面PFET的NFET。衬底中NFET的取向近似垂直于PFET的取向。提供了许多其他方面。

52. 发明申请

US20090244954A1 STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS 有权
标题翻译：改善存储容量对单一事件的可靠性的结构和方法
公开(公告)号：US20090244954A1
公开(公告)日：2009-10-01
申请号：US12055509
申请日：2008-03-26
申请人： Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
发明人： Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
IPC分类号： G11C11/40 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , G11C11/4125 , H01L27/0921 , H01L27/1104 , H01L29/66181 , H03K3/0375
摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).
摘要翻译：数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

53. 发明申请

US20090212362A1 SOI FIELD EFFECT TRANSISTOR WITH A BACK GATE FOR MODULATING A FLOATING BODY 失效
标题翻译：具有用于调制浮动体的后盖的SOI场效应晶体管
公开(公告)号：US20090212362A1
公开(公告)日：2009-08-27
申请号：US12036325
申请日：2008-02-25
申请人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
发明人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
IPC分类号： H01L21/84 , H01L29/786
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66772 , H01L29/78612 , H01L29/78648
摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.
摘要翻译：将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

54. 发明申请

US20090158226A1 HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS 有权
标题翻译：高密度，基于TRENCH的非易失性随机接入SONOS存储器用于SOC应用
公开(公告)号：US20090158226A1
公开(公告)日：2009-06-18
申请号：US11955940
申请日：2007-12-13
申请人： Herbert L. Ho , Jack A. Mandelman , Tak H. Ning , Yoichi Otani
发明人： Herbert L. Ho , Jack A. Mandelman , Tak H. Ning , Yoichi Otani
IPC分类号： G06F9/45
CPC分类号： H01L27/11568 , G11C16/0433 , H01L27/11565 , H01L27/1157
摘要： The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine readable medium. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 μm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.
摘要翻译：本发明提供了具有可随机存取的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元，以及包括体现在机器可读介质中的半导体存储器件的设计结构。在一个实施例中，提供了2-Tr SONOS单元，其中选择晶体管位于沟槽深度为1至2μm的沟槽结构，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

55. 发明授权

US07545253B2 Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
标题翻译：具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上
公开(公告)号：US07545253B2
公开(公告)日：2009-06-09
申请号：US12128100
申请日：2008-05-28
申请人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
IPC分类号： H01H85/08 , H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

56. 发明授权

US07531388B2 Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof 失效
标题翻译：具有窄宽度区域的电可编程熔丝结构被配置为增强电流拥挤及其制造方法
公开(公告)号：US07531388B2
公开(公告)日：2009-05-12
申请号：US11876942
申请日：2007-10-23
申请人： Roger A. Booth, Jr. , William R. Tonti , Jack A. Mandelman
发明人： Roger A. Booth, Jr. , William R. Tonti , Jack A. Mandelman
IPC分类号： H01L21/82 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.
摘要翻译：提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

57. 发明授权

US07525170B2 Pillar P-i-n semiconductor diodes 失效
标题翻译：支柱P-i-n半导体二极管
公开(公告)号：US07525170B2
公开(公告)日：2009-04-28
申请号：US11538557
申请日：2006-10-04
申请人： Louis Lu-Chen Hsu , Jack A. Mandelman , Kangguo Cheng
发明人： Louis Lu-Chen Hsu , Jack A. Mandelman , Kangguo Cheng
IPC分类号： H01L31/058
CPC分类号： H01L31/035281 , H01L27/1446 , H01L31/022408 , H01L31/022466 , H01L31/028 , H01L31/1804 , H01L31/1884 , Y02E10/547 , Y02P70/521
摘要： An arrangement of pillar shaped p-i-n diodes having a high aspect ration are formed on a semiconductor substrate. Each device is formed by an intrinsic or lightly doped region (i-region) positioned between a P+ region and an N+ region at each end of the pillar. The arrangement of pillar p-i-n diodes is embedded in an optical transparent medium. For a given surface area, more light energy is absorbed by the pillar arrangement of p-i-n diodes than by conventional planar p-i-n diodes. The pillar p-i-n diodes are preferably configured in an array formation to enable photons reflected from one pillar p-i-n diode to be captured and absorbed by another p-i-n diode adjacent to the first one, thereby optimizing the efficiency of energy conversion.
摘要翻译：在半导体衬底上形成具有高纵横比的柱状p-i-n二极管的布置。每个器件由位于柱的每个端部处的P +区域和N +区域之间的本征或轻掺杂区域（i区域）形成。柱p-i-n二极管的布置被嵌入在光学透明介质中。对于给定的表面积，p-i-n二极管的支柱排列比常规平面p-i-n二极管吸收更多的光能。支柱p-i-n二极管优选地被配置成阵列形成，以使得从一个柱p-i-n二极管反射的光子被与第一个p-i-n二极管相邻的另一个p-i-n二极管捕获和吸收，从而优化了能量转换的效率。

58. 发明授权

US07518191B1 Silicon on insulator devices having body-tied-to-source and methods of making 有权
标题翻译：硅绝缘体器件具有身体束缚源和制造方法
公开(公告)号：US07518191B1
公开(公告)日：2009-04-14
申请号：US12173280
申请日：2008-07-15
申请人： Thomas Dyer , Jack A. Mandelman , Keith Kwong Hon Wong , Chih-Chao Yang , Haining Sam Yang
发明人： Thomas Dyer , Jack A. Mandelman , Keith Kwong Hon Wong , Chih-Chao Yang , Haining Sam Yang
IPC分类号： H01L29/00
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L29/665 , H01L29/6659 , H01L29/66772 , H01L29/7835 , H01L29/78618
摘要： Silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a semiconductor device comprises: a gate conductor spaced above a semiconductor layer by a gate dielectric; dielectric spacers disposed laterally adjacent to sidewalls of the gate conductor; source and drain junctions laterally spaced apart by a body region in the semiconductor layer; and a conductive implant region comprising metallic species disposed in a bottom region of the semiconductor layer for electrically connecting the source junction to the body region, wherein a drain-side of the implant region is spaced apart from the body region and a source-side of the implant region contacts the body region.
摘要翻译：描述了具有身体绑定到源的绝缘体上硅器件。在一个实施例中，半导体器件包括：通过栅极电介质在半导体层之上间隔开的栅极导体; 电介质间隔件设置成横向邻近门导体的侧壁; 源极和漏极结，其横向间隔开半导体层中的体区; 以及导电植入区域，其包括设置在所述半导体层的底部区域中的金属物质，用于将所述源极接头与所述体区域电连接，其中所述植入区域的漏极侧与所述体区域间隔开，并且源极侧植入区域接触身体区域。

59. 发明授权

US07460003B2 Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
标题翻译：具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上
公开(公告)号：US07460003B2
公开(公告)日：2008-12-02
申请号：US11372387
申请日：2006-03-09
申请人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
IPC分类号： H01H85/08 , H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

60. 发明授权

US07439108B2 Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same 有权
标题翻译：具有不同晶体取向的共面绝缘体上硅（SOI）区域及其制造方法
公开(公告)号：US07439108B2
公开(公告)日：2008-10-21
申请号：US11155030
申请日：2005-06-16
申请人： Louis Lu-Chen Hsu , Jack A. Mandelman
发明人： Louis Lu-Chen Hsu , Jack A. Mandelman
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/045 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了半导体器件制造的第一种方法。第一种方法包括以下步骤：（1）提供衬底; 和（2）在基板上形成具有第一晶体取向的第一绝缘体上硅（SOI）区域，具有第二晶体取向的第二SOI区域和具有第三晶体取向的第三SOI区域。第一，第二和第三SOI区域是共面的。提供了许多其他方面。

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