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51. 发明授权

US08048474B2 Method of making nonvolatile memory cell containing carbon resistivity switching as a storage element by low temperature processing 有权
标题翻译：通过低温处理制造含有碳电阻率开关作为存储元件的非易失性存储单元的方法
公开(公告)号：US08048474B2
公开(公告)日：2011-11-01
申请号：US12222341
申请日：2008-08-07
申请人： Tanmay Kumar , Er-Xuan Ping , Alper Ilkbahar
发明人： Tanmay Kumar , Er-Xuan Ping , Alper Ilkbahar
IPC分类号： B05D5/12 , H01L21/20
CPC分类号： H01L45/04 , G11C13/00 , H01L27/2409 , H01L45/1233 , H01L45/149 , H01L45/1608
摘要： A method of making a nonvolatile memory cell includes forming a steering element and forming a carbon resistivity switching material storage element by coating a carbon containing colloid.
摘要翻译：制造非易失性存储单元的方法包括：通过涂覆含碳胶体形成转向元件并形成碳电阻率切换材料储存元件。

52. 发明授权

US07759666B2 3D R/W cell with reduced reverse leakage 有权
标题翻译： 3D R / W电池减少反向泄漏
公开(公告)号：US07759666B2
公开(公告)日：2010-07-20
申请号：US11819989
申请日：2007-06-29
申请人： Tanmay Kumar , Christopher J. Petti
发明人： Tanmay Kumar , Christopher J. Petti
IPC分类号： H01L29/02
CPC分类号： H01L27/24 , G11C13/0004
摘要： A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read/write switching element.
摘要翻译：非易失性存储器件包括半导体二极管操作元件和半导体读/写开关元件。

53. 发明授权

US07706169B2 Large capacity one-time programmable memory cell using metal oxides 失效
标题翻译：大容量一次性可编程存储单元，使用金属氧化物
公开(公告)号：US07706169B2
公开(公告)日：2010-04-27
申请号：US12005277
申请日：2007-12-27
申请人： Tanmay Kumar
发明人： Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C11/5692 , G11C13/0007 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0078 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/72
摘要： A method of programming a nonvolatile memory device includes (i) providing a nonvolatile memory cell comprising a diode in series with at least one metal oxide, (ii) applying a first forward bias to change a resistivity state of the metal oxide from a first state to a second state; (iii) applying a second forward bias to change a resistivity state of the metal oxide from a second state to a third state; and (iv) applying a third forward bias to change a resistivity state of the metal oxide from a third state to a fourth state. The fourth resistivity state is higher than the third resistivity state, the third resistivity state is lower than the second resistivity state, and the second resistivity state is lower than the first resistivity state.
摘要翻译：非易失性存储器件的编程方法包括：（i）提供包括与至少一种金属氧化物串联的二极管的非易失性存储单元，（ii）施加第一正向偏压以从第一状态改变金属氧化物的电阻率状态到第二个状态（iii）施加第二正向偏压以将金属氧化物的电阻率状态从第二状态改变到第三状态; 和（iv）施加第三正向偏压以将金属氧化物的电阻率状态从第三状态改变到第四状态。第四电阻率状态高于第三电阻率状态，第三电阻率状态低于第二电阻率状态，第二电阻率状态低于第一电阻率状态。

54. 发明申请

US20090258462A1 METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS 有权
标题翻译：通过连接多晶硅层形成掺杂多晶硅的方法
公开(公告)号：US20090258462A1
公开(公告)日：2009-10-15
申请号：US12489214
申请日：2009-06-22
申请人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
发明人： Michael W. Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew J. Walker , Tanmay Kumar
IPC分类号： H01L21/82
CPC分类号： H01L27/12 , H01L21/28282 , H01L21/84 , H01L23/535 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
摘要翻译：本发明提供了连接在不同高度形成的导电多晶硅层的多晶硅通孔。多晶硅通孔有利地用于电荷存储晶体管的单片三维存储器阵列中。根据本发明的多晶硅通孔可以用于例如将电荷存储晶体管存储单元的第一器件电平的沟道层连接到形成在第一器件电平之上的这样的单元的第二器件层的沟道层。类似地，根据本发明的通孔可用于将电荷存储晶体管存储单元的第一器件电平的字线连接到这种单元的第二器件层的沟道层。

55. 发明授权

US07553611B2 Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure 有权
标题翻译：掩盖重复的覆盖和对准标记，以允许在垂直结构中重复使用光掩模
公开(公告)号：US07553611B2
公开(公告)日：2009-06-30
申请号：US11097496
申请日：2005-03-31
申请人： Yung-Tin Chen , Christopher J Petti , Steven J Radigan , Tanmay Kumar
发明人： Yung-Tin Chen , Christopher J Petti , Steven J Radigan , Tanmay Kumar
IPC分类号： G03C5/00 , G03C1/00
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： In formation of monolithic three dimensional memory arrays, a photomask may be used more than once. Reuse of a photomask creates second, third or more instances of reference marks used by the stepper to achieve alignment (alignment marks) and to measure alignment achieved (overlay marks) directly above prior instances of the same reference mark. The prior instances of the same reference mark may cause interference with the present instance of the reference mark, complicating alignment and measurement. Using the methods of the present invention, blocking structure is created vertically interposed between subsequent instances of the same reference mark, preventing interference.
摘要翻译：在形成单片三维存储器阵列时，可以使用光掩模多于一次。重新使用光掩模创建步进器使用的第二，第三或更多个参考标记实例，以实现对齐（对齐标记）并且直接在相同参考标记的先前实例之上测量对齐（覆盖标记）。相同参考标记的先前实例可能引起对参考标记的当前实例的干扰，使对准和测量复杂化。使用本发明的方法，垂直插入相同参考标记的后续实例之间的阻挡结构，以防止干扰。

56. 发明授权

US07492630B2 Systems for reverse bias trim operations in non-volatile memory 有权
标题翻译：用于非易失性存储器中的反向偏置调整操作的系统
公开(公告)号：US07492630B2
公开(公告)日：2009-02-17
申请号：US11461431
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Tanmay Kumar
发明人： Roy E. Scheuerlein , Tanmay Kumar
IPC分类号： G11C13/04
CPC分类号： G11C8/08 , G11C5/02 , G11C11/56 , G11C13/0023 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C17/16 , G11C17/18 , G11C2213/71 , G11C2213/72
摘要： A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.
摘要翻译：公开了一种用于非易失性存储器系统的复位状态的反偏压调整操作。包括电阻变化元件的非易失性存储单元经历反向偏置复位操作，以在第二电阻电平下将其电阻从第一电阻上的设定状态改变为复位状态。复位的一组单元格中的某些存储单元可能被重新设置为超出复位状态的目标电平的电阻水平。第二反向偏压被施加到存储器单元组，以将每个单元的电阻移动到复位状态的目标电平。与用于复位操作相比较小的反向偏压可以将电池的电阻转移回设定电平并脱离它们的深度复位状态。操作是自限制的，因为细胞在达到目标水平时停止其阻力位移。未重新设置的单元格不受影响。

57. 发明申请

US20090001347A1 3D R/W cell with reduced reverse leakage 有权
标题翻译： 3D R / W电池减少反向泄漏
公开(公告)号：US20090001347A1
公开(公告)日：2009-01-01
申请号：US11819989
申请日：2007-06-29
申请人： Tanmay Kumar , Christopher J. Petti
发明人： Tanmay Kumar , Christopher J. Petti
IPC分类号： H01L45/00
CPC分类号： H01L27/24 , G11C13/0004
摘要： A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read/write switching element.
摘要翻译：非易失性存储器件包括半导体二极管操作元件和半导体读/写开关元件。

58. 发明申请

US20080316808A1 Nonvolatile memory device containing carbon or nitrogen doped diode 失效
标题翻译：包含碳或氮掺杂二极管的非易失性存储器件
公开(公告)号：US20080316808A1
公开(公告)日：2008-12-25
申请号：US11819042
申请日：2007-06-25
申请人： S. Brad Herner , Mark H. Clark , Tanmay Kumar
发明人： S. Brad Herner , Mark H. Clark , Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C11/36
摘要： A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.
摘要翻译：非易失性存储器件包括至少一个非易失性存储单元，其包括硅，锗或硅 - 锗二极管，其掺杂有浓度大于不可避免的杂质水平浓度的碳或氮中的至少一种。

59. 发明申请

US20080025077A1 SYSTEMS FOR CONTROLLED PULSE OPERATIONS IN NON-VOLATILE MEMORY 有权
标题翻译：在非易失性存储器中控制脉冲运行的系统
公开(公告)号：US20080025077A1
公开(公告)日：2008-01-31
申请号：US11461399
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Tanmay Kumar
发明人： Roy E. Scheuerlein , Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C5/145 , G11C5/02 , G11C8/08 , G11C13/0023 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C17/16 , G11C17/18 , G11C2213/71 , G11C2213/72
摘要： A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments. These controlled pulse-based operations can be used to set memory cells to a lower resistance state or reset memory cells to a higher resistance state in various embodiments.
摘要翻译：提供了一种无源元件存储器件，其包括由与转向元件串联的状态改变元件构成的存储单元。受控脉冲操作用于执行与存储器单元阵列中的置位和复位操作相关的电阻变化。在一个实施例中，通过对所选择的第一阵列线施加正电压脉冲同时向所选择的第二阵列线施加负电压脉冲，将阵列中的选定存储单元切换到目标电阻状态。可以增加电压脉冲的幅度，同时施加以有效和安全地切换具有不同操作特性的电池的电阻。在实施例中，电池经受反向偏置以降低泄漏电流并增加带宽。在一些实施例中，电压脉冲的幅度和持续时间与在选择的存储器单元上施加的电流一起被控制。这些受控的基于脉冲的操作可以用于在各种实施例中将存储器单元设置为较低的电阻状态或将存储器单元重置为更高的电阻状态。

60. 发明申请

US20080013364A1 Method of making non-volatile memory cell with embedded antifuse 有权
标题翻译：制造具有嵌入式反熔丝的非易失性存储单元的方法
公开(公告)号：US20080013364A1
公开(公告)日：2008-01-17
申请号：US11819595
申请日：2007-06-28
申请人： Tanmay Kumar , S. Herner
发明人： Tanmay Kumar , S. Herner
IPC分类号： G11C11/00 , H01L21/336
CPC分类号： G11C5/02 , G11C11/39 , G11C11/5692 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0676
摘要： A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion, and forming a second electrode over the at least one nonvolatile memory cell.
摘要翻译：制造非易失性存储器件的方法包括形成第一电极，形成至少一个非易失性存储单元，该非易失性存储单元包括第一二极管部分，第二二极管部分和将第一二极管部分与第二二极管部分分离的反熔丝，以及形成第二电极在所述至少一个非易失性存储单元上。

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