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51. 发明授权

US08586423B2 Silicon controlled rectifier with stress-enhanced adjustable trigger voltage 有权
公开(公告)号：US08586423B2
公开(公告)日：2013-11-19
申请号：US13168232
申请日：2011-06-24
申请人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas Stricker
发明人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas Stricker
IPC分类号： H01L21/02
CPC分类号： H01L29/7315 , G06F17/5063 , H01L27/0262 , H01L29/66393 , H01L29/7436
摘要： Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

52. 发明申请

US20130277753A1 BICMOS DEVICES ON ETSOI 审中-公开
标题翻译： BICMOS设备在ETSOI
公开(公告)号：US20130277753A1
公开(公告)日：2013-10-24
申请号：US13451806
申请日：2012-04-20
申请人： William F. Clark, JR. , Qizhi Liu , Robert Mark Rassel , Yun Shi
发明人： William F. Clark, JR. , Qizhi Liu , Robert Mark Rassel , Yun Shi
IPC分类号： H01L27/088 , G06F17/50 , H01L21/8249
CPC分类号： H01L21/84 , H01L21/8249 , H01L27/0623 , H01L27/1203
摘要： A BiCMOS device structure, method of manufacturing the same and design structure thereof are provided. The BiCMOS device structure includes a substrate having a layer of semiconductor material upon an insulating layer. The BiCMOS device structure further includes a bipolar junction transistor structure formed in a first region of the substrate having an extrinsic base layer formed at least partially from a portion of the layer of semiconductor material.
摘要翻译：提供BiCMOS器件结构，其制造方法及其设计结构。 BiCMOS器件结构包括在绝缘层上具有半导体材料层的衬底。 BiCMOS器件结构还包括形成在衬底的第一区域中的双极结型晶体管结构，其具有至少部分地由半导体材料层的一部分形成的非本征基极层。

53. 发明授权

US08492866B1 Isolated Zener diode 有权
标题翻译：隔离齐纳二极管
公开(公告)号：US08492866B1
公开(公告)日：2013-07-23
申请号：US13345881
申请日：2012-01-09
申请人： Frederick G. Anderson , Natalie B. Feilchenfeld , David L. Harmon , Richard A. Phelps , Yun Shi , Michael J. Zierak
发明人： Frederick G. Anderson , Natalie B. Feilchenfeld , David L. Harmon , Richard A. Phelps , Yun Shi , Michael J. Zierak
IPC分类号： H01L29/861 , H01L31/107 , H01L29/30 , H01L29/866 , H01L29/34 , H01L29/74 , H01L31/111 , H01L29/73 , H01L29/739 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/00 , H01L29/864
CPC分类号： H01L29/866 , H01L21/76 , H01L21/76283 , H01L27/0255 , H01L29/66106
摘要： Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.
摘要翻译：公开了一种齐纳二极管，其具有作为阴极接触区域相对于相邻阴极和阳极阱区域之间的界面的位置的函数的可分级反向偏压击穿电压（Vb）。具体地，阴极和阳极接触区域被定位成与相应的阴极和阳极阱区域相邻，并进一步被隔离区域分离。然而，当阳极接触区域完全包含在阳极阱区域内时，阴极接触区域的一端横向延伸到阳极阱区域中。为了选择性地调节二极管的Vb（例如，增加长度减小二极管的Vb，反之亦然），可以预定该端的长度。还公开了一种集成电路，其结合具有不同反向偏压击穿电压的二极管的多个实例，形成二极管的方法和二极管的设计结构。

54. 发明申请

US20120284111A1 MULTI-METRIC TRENDING STORYBOARD 审中-公开
标题翻译：多媒体趋势故事板
公开(公告)号：US20120284111A1
公开(公告)日：2012-11-08
申请号：US13098794
申请日：2011-05-02
申请人： Yun Shi , Haik E. Babaian , Dong Chen , Anand Edwin
发明人： Yun Shi , Haik E. Babaian , Dong Chen , Anand Edwin
IPC分类号： G06Q30/00
CPC分类号： G06Q30/0241
摘要： A graphical user interface for displaying internet advertising metrics and comparisons of internet advertising metrics is provided. The graphical user interface comprises a trending display area that displays a plurality of trending graphs in the same viewable area. Each trending graph displays a different internet advertising metric and is configured to display a plurality of internet advertising trending comparisons. As well, a detail display area displays a detail view of at least one of the trending graphs. The detail view is in the same viewable area as the plurality of trending graphs.
摘要翻译：提供了一种用于显示互联网广告指标和互联网广告指标比较的图形用户界面。图形用户界面包括在同一可视区域中显示多个趋势图的趋势显示区域。每个趋势图显示不同的互联网广告指标，并被配置为显示多个互联网广告趋势比较。同样，细节显示区域显示至少一个趋势图的详细视图。细节视图与多个趋势图在同一可视区域。

55. 发明申请

US20120132994A1 HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICE 审中-公开
标题翻译：高压半导体绝缘体器件
公开(公告)号：US20120132994A1
公开(公告)日：2012-05-31
申请号：US12955088
申请日：2010-11-29
申请人： William F. Clark, JR. , Yun Shi
发明人： William F. Clark, JR. , Yun Shi
IPC分类号： H01L27/12 , H01L21/322
CPC分类号： H01L21/84 , H01L27/1203
摘要： Embodiments of the present invention relate generally to semiconductor devices and, more particularly, to a structure for high-voltage (HV) semiconductor-on-insulator (SOI) devices and methods for their formation. In one embodiment, the invention provides a semiconductor-on-insulator (SOI) device comprising: a substrate; an insulator layer atop the substrate; a polysilicon layer atop the insulator layer; a device layer atop the polysilicon layer, the device layer comprising: a P-well; an N-well; and an undoped silicon region between the P-well and the N-well; and a trench isolation adjacent one of the P-well and the N-well and extending through the device layer and the polysilicon layer to the insulator layer.
摘要翻译：本发明的实施例大体上涉及半导体器件，更具体地，涉及一种用于高电压（HV）绝缘体上半导体（SOI）器件的结构及其形成方法。在一个实施例中，本发明提供了一种绝缘体上半导体器件（SOI）器件，包括：衬底; 位于基板顶部的绝缘体层; 在绝缘体层顶上的多晶硅层; 所述多晶硅层顶部的器件层，所述器件层包括：P阱; 一个N井; 以及P阱和N阱之间的未掺杂的硅区; 以及邻近P阱和N阱中的一个的沟槽隔离并延伸穿过器件层和多晶硅层到绝缘体层。

56. 发明授权

US08120110B2 Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate 有权
标题翻译：在SOI衬底上包括高性能FET和高电压FET的半导体结构
公开(公告)号：US08120110B2
公开(公告)日：2012-02-21
申请号：US12188381
申请日：2008-08-08
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

57. 发明申请

US20110291171A1 VARACTOR 审中-公开
标题翻译：变量
公开(公告)号：US20110291171A1
公开(公告)日：2011-12-01
申请号：US13050043
申请日：2011-03-17
申请人： John J. Pekarik , William F. Clark, JR. , Robert J. Gauthier, JR. , Yun Shi , Yanli Zhang
发明人： John J. Pekarik , William F. Clark, JR. , Robert J. Gauthier, JR. , Yun Shi , Yanli Zhang
IPC分类号： H01L29/92 , H01L21/8234
CPC分类号： H01L29/93 , H01L27/0808 , H01L27/0811 , H01L29/78
摘要： A variable capacitance device including a plurality of FETs, the sources and drains of each FET being coupled to a first terminal, the gates of each FET being coupled to a second terminal, the capacitance of said device between said first and second terminals varying as a function of the voltage across said terminals, the device further including a biasing providing a respective backgate bias voltage to each the FETs setting a respective gate threshold voltage thereof. The aggregate V-C characteristic can be tuned as desired, either at design time or dynamically. The greater the number of FETs forming the varactor, the greater the number of possible Vt values that can be individually set, so that arbitrary V-C characteristics can be more closely approximated.
摘要翻译：一种包括多个FET的可变电容器件，每个FET的源极和漏极耦合到第一端子，每个FET的栅极耦合到第二端子，所述器件在所述第一和第二端子之间的电容变化为所述器件还包括偏置电路，为每个FET提供相应的背栅极偏置电压，从而设置其相应的栅极阈值电压。可以在设计时或动态地根据需要调整总体V-C特性。形成变容二极管的FET数量越多，可以单独设置的可能的Vt值的数量就越多，从而可以更接近任意的V-C特性。

58. 发明授权

US07700428B2 Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory 失效
标题翻译：制造用作非易失性随机存取存储器中的存储器单元的器件结构的方法
公开(公告)号：US07700428B2
公开(公告)日：2010-04-20
申请号：US12117950
申请日：2008-05-09
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier , Jed H. Rankin , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier , Jed H. Rankin , Yun Shi , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L29/7881 , H01L27/1203 , H01L29/66825
摘要： Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body.
摘要翻译：制造用作非易失性随机存取存储器中的存储单元的器件结构的方法。该方法包括在绝缘层上形成具有分开且并置的关系的第一和第二半导体本体，掺杂第一半导体本体以形成源极和漏极，并且部分地移除第二半导体本体以限定邻近第一半导体体的通道。该方法还包括在第一半导体本体的沟道与浮栅之间形成第一电介质层，在浮置栅电极的顶表面上形成第二电介质层，在第二电介质层上形成控制栅电极，与浮栅电极配合，以控制第一半导体体的沟道中的载流子流动。

59. 发明申请

US20100041202A1 Methods For Forming Back-End-Of-Line Resistive Semiconductor Structures 有权
标题翻译：形成后端电阻半导体结构的方法
公开(公告)号：US20100041202A1
公开(公告)日：2010-02-18
申请号：US12191633
申请日：2008-08-14
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
IPC分类号： H01L21/02
CPC分类号： H01L23/5228 , H01L21/76816 , H01L23/5226 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.
摘要翻译：在一个实施例中，嵌入在第二介电层中的第二金属线覆盖在嵌入第一介电层中的第一金属线上。覆盖第一金属线的第二电介质层的一部分使用光致抗蚀剂凹陷，第二金属线作为蚀刻掩模。在凹槽内形成掺杂半导体衬垫，以在第一金属线和第二金属线之间提供电阻连接。在另一个实施例中，第一金属线和第二金属线嵌入在电介质层中。使用光致抗蚀剂和第一和第二金属线作为蚀刻掩模来凹入与第一和第二金属线横向邻接的电介质层的区域。掺杂半导体衬垫形成在第一和第二金属线的侧壁上，提供第一和第二金属线之间的电阻连接。

60. 发明申请

US20080290524A1 THROUGH VIA IN ULTRA HIGH RESISTIVITY WAFER AND RELATED METHODS 有权
标题翻译：通过超高电阻率波形和相关方法
公开(公告)号：US20080290524A1
公开(公告)日：2008-11-27
申请号：US11753617
申请日：2007-05-25
申请人： Louis D. Lanzerotti , Max G. Levy , Yun Shi , Steven H. Voldman
发明人： Louis D. Lanzerotti , Max G. Levy , Yun Shi , Steven H. Voldman
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through via in an ultra high resistivity wafer and related methods are disclosed. A method for forming a through via comprises: providing a semiconductor wafer including a first silicon layer, a buried dielectric layer, and a substrate; forming a device on the first silicon; and forming a via from a side of the substrate opposite to the buried dielectric layer and through the substrate.
摘要翻译：公开了一种超高电阻率晶圆的通孔和相关方法。形成通孔的方法包括：提供包括第一硅层，埋入介质层和基底的半导体晶片; 在第一硅上形成器件; 以及从所述衬底的与所述掩埋介电层相对的一侧并通过所述衬底形成通孔。

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