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1. 发明授权

US07485965B2 Through via in ultra high resistivity wafer and related methods 有权
标题翻译：通过超高电阻率晶圆及相关方法
公开(公告)号：US07485965B2
公开(公告)日：2009-02-03
申请号：US11753617
申请日：2007-05-25
申请人： Louis D. Lanzerotti , Max G. Levy , Yun Shi , Steven H. Voldman
发明人： Louis D. Lanzerotti , Max G. Levy , Yun Shi , Steven H. Voldman
IPC分类号： H01L27/01
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through via in an ultra high resistivity wafer and related methods are disclosed. A method for forming a through via comprises: providing a semiconductor wafer including a first silicon layer, a buried dielectric layer, and a substrate; forming a device on the first silicon; and forming a via from a side of the substrate opposite to the buried dielectric layer and through the substrate. Also disclosed is a method for providing a wafer varied resistivity using the through vias and buried dielectric.
摘要翻译：公开了一种超高电阻率晶圆的通孔和相关方法。形成通孔的方法包括：提供包括第一硅层，埋入介质层和基底的半导体晶片; 在第一硅上形成器件; 以及从所述衬底的与所述掩埋介电层相对的一侧并通过所述衬底形成通孔。还公开了一种使用通孔和埋入电介质提供晶片变化的电阻率的方法。

2. 发明申请

US20080290524A1 THROUGH VIA IN ULTRA HIGH RESISTIVITY WAFER AND RELATED METHODS 有权
标题翻译：通过超高电阻率波形和相关方法
公开(公告)号：US20080290524A1
公开(公告)日：2008-11-27
申请号：US11753617
申请日：2007-05-25
申请人： Louis D. Lanzerotti , Max G. Levy , Yun Shi , Steven H. Voldman
发明人： Louis D. Lanzerotti , Max G. Levy , Yun Shi , Steven H. Voldman
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through via in an ultra high resistivity wafer and related methods are disclosed. A method for forming a through via comprises: providing a semiconductor wafer including a first silicon layer, a buried dielectric layer, and a substrate; forming a device on the first silicon; and forming a via from a side of the substrate opposite to the buried dielectric layer and through the substrate.
摘要翻译：公开了一种超高电阻率晶圆的通孔和相关方法。形成通孔的方法包括：提供包括第一硅层，埋入介质层和基底的半导体晶片; 在第一硅上形成器件; 以及从所述衬底的与所述掩埋介电层相对的一侧并通过所述衬底形成通孔。

3. 发明授权

US07842580B2 Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications 有权
标题翻译： SOI / RF SiGe应用的超高电阻率晶圆掩埋电感的结构和方法
公开(公告)号：US07842580B2
公开(公告)日：2010-11-30
申请号：US12122754
申请日：2008-05-19
申请人： Max G. Levy , Steven H. Voldman
发明人： Max G. Levy , Steven H. Voldman
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L27/0617 , H01L27/08 , H01L28/10
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括高电阻率衬底和直接形成在高电阻率衬底中且在它们之间没有绝缘层的埋地电感器。

4. 发明申请

US20090283854A1 Design Structure and Method for Buried Inductors for Ultra-High Resistivity Wafers for SOI/RF SIGE Applications 有权
标题翻译：用于SOI / RF SIGE应用的超高电阻率晶片的埋入式电感器的设计结构和方法
公开(公告)号：US20090283854A1
公开(公告)日：2009-11-19
申请号：US12122754
申请日：2008-05-19
申请人： Max G. Levy , Steven H. Voldman
发明人： Max G. Levy , Steven H. Voldman
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L27/1203 , H01L27/0617 , H01L27/08 , H01L28/10
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括高电阻率衬底和直接形成在高电阻率衬底中且在它们之间没有绝缘层的埋地电感器。

5. 发明授权

US08487379B2 Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications 有权
标题翻译： SOI / RF SiGe应用的超高电阻率晶圆掩埋电感的结构和方法
公开(公告)号：US08487379B2
公开(公告)日：2013-07-16
申请号：US13453426
申请日：2012-04-23
申请人： Max G. Levy , Steven H. Voldman
发明人： Max G. Levy , Steven H. Voldman
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L27/0617 , H01L27/08 , H01L28/10
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括高电阻率衬底和直接形成在高电阻率衬底中且在它们之间没有绝缘层的埋地电感器。

6. 发明授权

US08188570B2 Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications 有权
标题翻译： SOI / RF SiGe应用的超高电阻率晶圆掩埋电感的结构和方法
公开(公告)号：US08188570B2
公开(公告)日：2012-05-29
申请号：US12875398
申请日：2010-09-03
申请人： Max G. Levy , Steven H. Voldman
发明人： Max G. Levy , Steven H. Voldman
IPC分类号： H01L27/08
CPC分类号： H01L27/1203 , H01L27/0617 , H01L27/08 , H01L28/10
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括高电阻率衬底和直接形成在高电阻率衬底中且在它们之间没有绝缘层的埋地电感器。

7. 发明授权

US06361402B1 Method for planarizing photoresist 失效
标题翻译：平版化光刻胶的方法
公开(公告)号：US06361402B1
公开(公告)日：2002-03-26
申请号：US09427492
申请日：1999-10-26
申请人： Donald F. Canaperi , Rangarajan Jagannathan , Mahadevaiyer Krishnan , Max G. Levy , Uma Satyendra , Matthew Sendelbach , James A. Tornello , William Wille
发明人： Donald F. Canaperi , Rangarajan Jagannathan , Mahadevaiyer Krishnan , Max G. Levy , Uma Satyendra , Matthew Sendelbach , James A. Tornello , William Wille
IPC分类号： B24B100
CPC分类号： B24B37/0056 , B24B37/044 , H01L21/31053 , H01L21/76819
摘要： A method for polishing an object having a layer of photoresist, the method, employing the following steps: a) applying a layer of slurry on an a layer of photoresist on an object having a first and a second side, the layer of photoresist on one of the first and second side, the object having a center axis perpendicular to the first and second side; b) contacting the layer of slurry with a pad having a first and second side, the first side of the pad exerting a force on the slurry.
摘要翻译：一种用于抛光具有光致抗蚀剂层的物体的方法，该方法采用以下步骤：a）在具有第一和第二侧的物体上的一层光致抗蚀剂上施加一层浆料，一层光致抗蚀剂所述第一和第二侧的物体具有垂直于第一和第二侧的中心轴; b）使浆料层与具有第一和第二侧的垫接触，垫的第一侧在浆料上施加力。

8. 发明申请

US20110127529A1 SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：用于减少谐波的硅绝缘体（SOI）结构和形成结构的方法
公开(公告)号：US20110127529A1
公开(公告)日：2011-06-02
申请号：US12627343
申请日：2009-11-30
申请人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L21/02488 , H01L21/2652 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.
摘要翻译：公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。本文还公开了用于形成这种半导体结构的方法的实施例。

9. 发明授权

US06388305B1 Electrically programmable antifuses and methods for forming the same 有权
标题翻译：电子可编程反熔丝及其形成方法
公开(公告)号：US06388305B1
公开(公告)日：2002-05-14
申请号：US09466495
申请日：1999-12-17
申请人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
发明人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
IPC分类号： H01L2900
CPC分类号： H01L21/763 , H01L23/5252 , H01L27/10861 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a first dielectric material lining the interior surface and a second dielectric material filling the lined trench. The second logic element further comprises a dielectric layer formed over a portion of the first layer and contacting the first dielectric material lining the trench at a merge location; and an electrode extending over a portion of both the dielectric layer and the filled trench. The second logic element is configured so that a predetermined voltage or higher applied between the electrode and the first layer causes a breakdown near the merge location.
摘要翻译：首先，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该第一导电类型的半导体衬底包括在衬底的表面下面的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。第二次，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该半导体衬底包括形成在衬底的表面中的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。沟槽包括内表面，衬在内表面的第一电介质材料和填充衬里沟槽的第二电介质材料。第二逻辑元件还包括形成在第一层的一部分上并且在合并位置处接触衬套在沟槽上的第一介电材料的电介质层; 以及在电介质层和填充沟槽的一部分上延伸的电极。第二逻辑元件被配置为使得施加在电极和第一层之间的预定电压或更高的电压导致合并位置附近的击穿。

10. 发明授权

US06812122B2 Method for forming a voltage programming element 有权
标题翻译：用于形成电压编程元件的方法
公开(公告)号：US06812122B2
公开(公告)日：2004-11-02
申请号：US10095889
申请日：2002-03-12
申请人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
发明人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
IPC分类号： H01L2144
CPC分类号： H01L21/763 , H01L23/5252 , H01L27/10861 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： Method for forming a first one time, voltage programmable logic element in a semiconductor substrate of first conductivity type, forming a first layer beneath a surface of the substrate, the first layer having a second conductivity type. A trench is formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench.
摘要翻译：用于形成第一导电类型的半导体衬底中的第一次电压可编程逻辑元件的方法，在所述衬底的表面下方形成第一层，所述第一层具有第二导电类型。沟槽通过表面形成并穿过第一层。沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。

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