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51. 发明授权

US07208768B2 Electroluminescent device 失效
标题翻译：电致发光器件
公开(公告)号：US07208768B2
公开(公告)日：2007-04-24
申请号：US10836669
申请日：2004-04-30
申请人： Yoshi Ono , Wei Gao , John F. Conley, Jr. , Osamu Nishio , Keizo Sakiyama
发明人： Yoshi Ono , Wei Gao , John F. Conley, Jr. , Osamu Nishio , Keizo Sakiyama
IPC分类号： H01L27/15
CPC分类号： H01L33/28 , H01L33/18 , H01L33/34 , Y10S977/95
摘要： A method is provided for forming an electroluminescent device. The method comprises: providing a type IV semiconductor material substrate; forming a p+/n+ junction in the substrate, typically a plurality of interleaved p+/n+ junctions are formed; and, forming an electroluminescent layer overlying the p+/n+ junction(s) in the substrate. The type IV semiconductor material substrate can be Si, C, Ge, SiGe, or SiC. For example, the substrate can be Si on insulator (SOI), bulk Si, Si on glass, or Si on plastic. The electroluminescent layer can be a material such as nanocrystalline Si, nanocrystalline Ge, fluorescent polymers, or type II–VI materials such as ZnO, ZnS, ZnSe, CdSe, and CdS. In some aspect, the method further comprises forming an insulator film interposed between the substrate and the electroluminescent layer. In another aspect, the method comprises forming a conductive electrode overlying the electroluminescent layer.
摘要翻译：提供了形成电致发光器件的方法。该方法包括：提供IV型半导体材料基板; 在衬底中形成p + / n +结，通常形成多个交错的p + / n +结; 并且形成覆盖衬底中的p + / n +结的电致发光层。 IV型半导体材料基板可以是Si，C，Ge，SiGe或SiC。例如，衬底可以是绝缘体上的硅（SOI），玻璃上的体积Si，Si或塑料上的Si。电致发光层可以是诸如纳米晶体Si，纳米晶体Ge，荧光聚合物或诸如ZnO，ZnS，ZnSe，CdSe和CdS的II-VI族材料的材料。在一些方面，所述方法还包括形成介于基片和电致发光层之间的绝缘膜。另一方面，该方法包括形成覆盖电致发光层的导电电极。

52. 发明授权

US07129552B2 MOSFET structures with conductive niobium oxide gates 有权
标题翻译：具有导电铌氧化物栅极的MOSFET结构
公开(公告)号：US07129552B2
公开(公告)日：2006-10-31
申请号：US10677006
申请日：2003-09-30
申请人： Wei Gao , Yoshi Ono
发明人： Wei Gao , Yoshi Ono
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/66583 , H01L21/28088 , H01L21/28194 , H01L29/4966 , H01L29/517 , H01L29/78
摘要： MOSFET gate structures are provided comprising a niobium monoxide gate, overlying a gate dielectric. The niobium monoxide gate may have a low work function suitable for use as an NMOS gate.
摘要翻译：提供包括覆盖栅极电介质的铌氧化物栅极的MOSFET栅极结构。铌氧化物栅可能具有适合用作NMOS栅极的低功函数。

53. 发明申请

US20060211267A1 Silicon oxide thin-films with embedded nanocrystalline silicon 有权
公开(公告)号：US20060211267A1
公开(公告)日：2006-09-21
申请号：US11418273
申请日：2006-05-04
申请人： Pooran Joshi , Tingkai Li , Yoshi Ono , Apostolos Voutsas , John Hartzell
发明人： Pooran Joshi , Tingkai Li , Yoshi Ono , Apostolos Voutsas , John Hartzell
IPC分类号： H01L21/31
CPC分类号： H01L21/31608 , C23C16/30 , C23C16/401 , C23C16/402 , C23C16/505 , C23C16/56 , H01L21/02164 , H01L21/02274 , H01L21/02337 , H01L21/0234
摘要： A method is provided for forming a silicon oxide (SiOx) thin-film with embedded nanocrystalline silicon (Si). The method deposits SiOx, where x is in the range of 1 to 2, overlying a substrate, using a high-density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, the SiOx thin-film is embedded with nanocrystalline Si. The HD PECVD process may use an inductively coupled plasma (ICP) source, a substrate temperature of less than about 400° C., and an oxygen source gas with a silicon precursor. In one aspect, a hydrogen source gas and an inert gas are used, where the ratio of oxygen source gas to inert gas is in the range of about 0.02 to 5. The SiOx thin-film with embedded nanocrystalline Si typically has a refractive index in the range of about 1.6 to 2.2, with an extinction coefficient in the range of 0 to 0.5.

54. 发明申请

US20060180816A1 Wide wavelength range silicon electroluminescence device 审中-公开
标题翻译：宽波长范围的硅电致发光器件
公开(公告)号：US20060180816A1
公开(公告)日：2006-08-17
申请号：US11058505
申请日：2005-02-14
申请人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Hsu
发明人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Hsu
IPC分类号： H01L29/26
CPC分类号： H05B33/145
摘要： A method is provided for forming a Si electroluminescence (EL) device for emitting light at short wavelengths. The method comprises: providing a substrate; forming a first insulator layer overlying the substrate; forming a silicon-rich silicon oxide (SRSO) layer overlying the first insulator layer, embedded with nanocrystalline Si having a size in the range of 0.5 to 5 nm; forming a second insulator layer overlying the SRSO layer; and, forming a top electrode. Typically, the SRSO has a Si richness in the range of 5 to 40%. In one aspect, the SRSO layer is formed using a DC sputtering process. In another aspect, the SRSO formation step includes a rapid thermal annealing (RTA) process subsequent to depositing the SRSO. Likewise, thermal oxidation or plasma oxidation can be performed subsequent to the SRSO layer deposition. The size of Si nanocrystals is decreased in response to above-mentioned deposition, annealing, and oxidation processes.
摘要翻译：提供一种用于形成用于发射短波长的光的Si电致发光（EL）装置的方法。该方法包括：提供衬底; 形成覆盖所述衬底的第一绝缘体层; 形成覆盖在第一绝缘体层上的富硅氧化物（SRSO）层，其中嵌入尺寸在0.5至5nm范围内的纳米晶体Si; 形成覆盖所述SRSO层的第二绝缘体层; 并形成顶部电极。通常，SRSO的Si浓度范围为5〜40％。在一个方面，使用DC溅射工艺形成SRSO层。另一方面，SRSO形成步骤包括在沉积SRSO之后的快速热退火（RTA）工艺。同样地，可以在SRSO层沉积之后进行热氧化或等离子体氧化。响应于上述沉积，退火和氧化过程，Si纳米晶体的尺寸减小。

55. 发明申请

US20060160335A1 Rare earth element-doped silicon/silicon dioxide lattice structure 失效
标题翻译：稀土元素掺杂硅/二氧化硅晶格结构
公开(公告)号：US20060160335A1
公开(公告)日：2006-07-20
申请号：US11039463
申请日：2005-01-19
申请人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Hsu
发明人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Hsu
IPC分类号： H01L21/20
CPC分类号： C23C14/16 , C03C17/34 , C23C14/10 , C23C28/322 , C23C28/323 , C23C28/345 , C23C28/3455 , C23C28/42 , H01L21/02164 , H01L21/02266 , H01L21/0237 , H01L21/02532 , H01L21/02573 , H01L21/0259 , H01L21/02631 , H01L21/02667 , H01L21/31608 , H01L33/26
摘要： Provided are an electroluminescence (EL) device and corresponding method for forming a rare earth element-doped silicon (Si)/Si dioxide (SiO2) lattice structure. The method comprises: providing a substrate; DC sputtering a layer of amorphous Si overlying the substrate; DC sputtering a rare earth element; in response, doping the Si layer with the rare earth element; DC sputtering a layer of SiO2 overlying the rare earth-doped Si; forming a lattice structure; annealing; and, in response to the annealing, forming nanocrystals in the rare-earth doped Si having a grain size in the range of 1 to 5 nanometers (nm). In one aspect, the rare earth element and Si are co-DC sputtered. Typically, the steps of DC sputtering Si, DC sputtering the rare earth element, and DC sputtering the SiO2 are repeated 5 to 60 cycles, so that the lattice structure includes the plurality (5-60) of alternating SiO2 and rare earth element-doped Si layers.
摘要翻译：提供了一种用于形成稀土元素掺杂硅（Si）/二氧化硅（SiO 2）晶格结构的电致发光（EL）器件和相应的方法。该方法包括：提供衬底; DC溅射覆盖衬底的非晶硅层; 直流溅射稀土元素; 作为响应，用稀土元素掺杂Si层; DC溅射一层SiO 2，覆盖稀土掺杂的Si; 形成晶格结构; 退火; 并且响应于退火，在具有1至5纳米（nm）范围内的晶粒尺寸的稀土掺杂Si中形成纳米晶体。一方面，稀土元素和Si共溅射。通常，DC溅射Si，DC溅射稀土元素和DC溅射SiO 2的步骤重复5至60个循环，使得晶格结构包括多个（5-60）交替的SiO 2和稀土元素掺杂 Si层。

56. 发明授权

US07053009B2 Nanolaminate film atomic layer deposition method 有权
标题翻译： Naminaminate膜原子层沉积法
公开(公告)号：US07053009B2
公开(公告)日：2006-05-30
申请号：US11089947
申请日：2005-03-24
申请人： John F. Conley, Jr. , Yoshi Ono , Rajendra Solanki
发明人： John F. Conley, Jr. , Yoshi Ono , Rajendra Solanki
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/0228 , C23C16/40 , C23C16/45529 , C23C16/45531 , C23C16/56 , H01L21/02178 , H01L21/02181 , H01L21/022 , H01L21/02205 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： An atomic layer deposition method to deposit an oxide nanolaminate thin film is provided. The method employs a nitrate ligand in a first precursor as an oxidizer for a second precursor to form the oxide nanolaminates. Using a hafnium nitrate precursor and an aluminum precursor, the method is well suited for the deposition of a high k hafnium oxide/aluminum oxide nanolaminate dielectric for gate dielectric or capacitor dielectric applications on a hydrogen-terminated silicon surface.
摘要翻译：提供沉积氧化物Naminaminate薄膜的原子层沉积方法。该方法在第一前体中使用硝酸盐配体作为第二前体的氧化剂，以形成氧化物纳米级氨酸盐。使用硝酸铪前体和铝前体，该方法非常适合于在氢封端的硅表面上沉积栅极电介质或电容器电介质应用的高k铪氧化物/氧化铝纳米酸盐电介质。

57. 发明申请

US20060046204A1 Directly patternable microlens 审中-公开
标题翻译：直接图案化的微透镜
公开(公告)号：US20060046204A1
公开(公告)日：2006-03-02
申请号：US10931596
申请日：2004-08-31
申请人： Yoshi Ono , Wei-Wei Zhuang , Wei Gao , Bruce Ulrich
发明人： Yoshi Ono , Wei-Wei Zhuang , Wei Gao , Bruce Ulrich
IPC分类号： G02B3/00
CPC分类号： G02B3/0012
摘要： A method of forming a microlens structure using a patternable lens material is provided. An organic-inorganic hybrid polymer comprising titanium dioxide is exposed to light using a defocused mask image and then developed to produce a lens-shaped region.
摘要翻译：提供了使用可图案的透镜材料形成微透镜结构的方法。使用散焦的掩模图像将包含二氧化钛的有机 - 无机杂化聚合物暴露于光，然后显影以产生透镜形区域。

58. 发明授权

US06930059B2 Method for depositing a nanolaminate film by atomic layer deposition 有权
标题翻译：通过原子层沉积沉积Naminaminate膜的方法
公开(公告)号：US06930059B2
公开(公告)日：2005-08-16
申请号：US10376794
申请日：2003-02-27
申请人： John F. Conley, Jr. , Yoshi Ono , Rajendra Solanki
发明人： John F. Conley, Jr. , Yoshi Ono , Rajendra Solanki
IPC分类号： H01L21/205 , C23C16/40 , C23C16/44 , C23C16/455 , C23C16/56 , H01L21/28 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/49 , H01L29/51 , H01L21/31 , H01L21/469
CPC分类号： H01L21/0228 , C23C16/40 , C23C16/45529 , C23C16/45531 , C23C16/56 , H01L21/02178 , H01L21/02181 , H01L21/022 , H01L21/02205 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： An atomic layer deposition method to deposit an oxide nanolaminate thin film is provided. The method employs a nitrate ligand in a first precursor as an oxidizer for a second precursor to form the oxide nanolaminates. Using a hafnium nitrate precursor and an aluminum precursor, the method is well suited for the deposition of a high k hafnium oxide/aluminum oxide nanolaminate dielectric for gate dielectric or capacitor dielectric applications on a hydrogen-terminated silicon surface.
摘要翻译：提供沉积氧化物Naminaminate薄膜的原子层沉积方法。该方法在第一前体中使用硝酸盐配体作为第二前体的氧化剂，以形成氧化物纳米级氨酸盐。使用硝酸铪前体和铝前体，该方法非常适合于在氢封端的硅表面上沉积栅极电介质或电容器电介质应用的高k铪氧化物/氧化铝纳米酸盐电介质。

59. 发明申请

US20050136695A1 Thin film oxide interface 失效
标题翻译：薄膜氧化物界面
公开(公告)号：US20050136695A1
公开(公告)日：2005-06-23
申请号：US11046571
申请日：2005-01-28
申请人： Pooran Joshi , John Hartzell , Masahiro Adachi , Yoshi Ono
发明人： Pooran Joshi , John Hartzell , Masahiro Adachi , Yoshi Ono
IPC分类号： H01L21/316 , H01L21/336 , H01L29/49 , H01L29/786 , H01L23/58 , H01L21/26 , H01L21/324 , H01L21/42 , H01L21/477
CPC分类号： H01L29/66757 , H01L29/4908 , H01L29/66772
摘要： An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.
摘要翻译：提供氧化物界面和制造氧化物界面的方法。该方法包括形成硅层和覆盖硅层的氧化物层。使用电感耦合等离子体源在低于400℃的温度下形成氧化物层。在该方法的一些方面，氧化物层的厚度大于20纳米（nm），折射率在1.45和1.47之间。在该方法的一些方面，通过等离子体氧化硅层形成氧化物层，以每分钟高达约4.4nm的速率产生等离子体氧化物（1分钟后）。在该方法的某些方面，使用高密度等离子体增强化学气相沉积（HD-PECVD）工艺来形成氧化物层。在该方法的一些方面，将硅和氧化物层结合到薄膜晶体管中。

60. 发明申请

US20050088898A1 Low power flash memory cell and method 审中-公开
标题翻译：低功耗闪存单元和方法
公开(公告)号：US20050088898A1
公开(公告)日：2005-04-28
申请号：US10976596
申请日：2004-10-29
申请人： Sheng Hsu , Yoshi Ono
发明人： Sheng Hsu , Yoshi Ono
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： H01L21/28194 , H01L21/76224 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/7883 , Y10S438/975
摘要： Flash memory cells are provided with a high-k material interposed between a floating polysilicon gate and a control gate. A tunnel oxide is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.
摘要翻译：闪存单元设置有插入在浮置多晶硅栅极和控制栅极之间的高k材料。在浮置多晶硅栅极和衬底之间插入隧道氧化物。还提供了形成闪存单元的方法，包括在衬底上形成第一多晶硅层。通过第一多晶硅层形成沟槽并进入衬底，并用氧化物层填充沟槽。在氧化物上沉积第二多晶硅层，使得沟槽内的第二多晶硅层的底部高于第一多晶硅层的底部，并且沟槽内的第二多晶硅层的顶部低于第一多晶硅的顶部层。然后可以使用CMP工艺将得到的结构平坦化。然后可以在第一多晶硅层上沉积高k电介质层。然后可以在高k电介质层上沉积第三多晶硅层，并使用光致抗蚀剂图案化以形成闪存栅极结构。在图案化期间，蚀刻暴露的第二多晶硅层。在完成去除第二多晶硅层时检测到蚀刻停止。保留第一多晶硅层的薄层，使用随后的选择性蚀刻工艺小心地去除。结合形成闪速存储器单元的过程，高k电介质层可以被图案化以允许形成非存储晶体管。

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