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51. 发明授权

US06730616B2 Versatile plasma processing system for producing oxidation resistant barriers 有权
标题翻译：用于生产抗氧化屏障的多功能等离子体处理系统
公开(公告)号：US06730616B2
公开(公告)日：2004-05-04
申请号：US10253338
申请日：2002-09-24
申请人： Scott R. Summerfelt
发明人： Scott R. Summerfelt
IPC分类号： H01L2131
CPC分类号： H01L21/76829 , H01L21/3144 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/7687 , H01L28/55 , H01L28/60
摘要： A versatile system for forming diffusion barriers in semiconductor processing that simplifies device processing, utilizing existing production compounds and materials while resulting in uniform and proper device structuring, is disclosed, providing a system using a reactive plasma to selectively form diffusion barriers and provide selective oxidation.
摘要翻译：公开了一种用于在半导体加工中形成扩散阻挡层的通用系统，其简化了器件加工，利用现有的生产化合物和材料，同时产生均匀且适当的器件结构，提供了使用反应性等离子体选择性地形成扩散阻挡层并提供选择性氧化的系统。

52. 发明授权

US06713342B2 FeRAM sidewall diffusion barrier etch 有权
标题翻译： FeRAM侧壁扩散阻挡蚀刻
公开(公告)号：US06713342B2
公开(公告)日：2004-03-30
申请号：US10282759
申请日：2002-10-29
申请人： Francis G. Celii , Scott R. Summerfelt , Tomoyuki Sakoda , Chiu Chi
发明人： Francis G. Celii , Scott R. Summerfelt , Tomoyuki Sakoda , Chiu Chi
IPC分类号： H01L218242
CPC分类号： H01L21/31122 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.
摘要翻译：本发明涉及一种形成FeRAM集成电路的方法，其包括在蚀刻底部电极扩散阻挡层之前形成侧壁扩散阻挡层。然后在底部电极扩散阻挡层之前蚀刻侧壁扩散阻挡层。在蚀刻下面的底部电极扩散阻挡层之前，在构图AlOx侧壁扩散阻挡层之前，蚀刻化学性质包括BCl 3 + Ar。 BCl3在相邻的电容器堆叠之间的电容器堆叠（例如TiAlN）和氮化物底部电极扩散阻挡层（例如，具有小的氧含量的TiAlON）的顶部上对下面的氮化物硬掩模具有良好的选择性是有效的。可以将Ar添加到蚀刻化学品中，因为所得到的表面（硬掩模和底部电极扩散屏障的顶部）更平滑。

53. 发明授权

US06596547B2 Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing 有权
标题翻译：通过金属有机化学气相沉积或其他处理防止PZT形成期间IrOx的还原的方法
公开(公告)号：US06596547B2
公开(公告)日：2003-07-22
申请号：US10036805
申请日：2001-12-21
申请人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
发明人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
IPC分类号： H01L2100
CPC分类号： H01L28/75 , C23C14/0084 , C23C14/08 , H01L28/55
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises decreasing a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. The method comprises forming an oxygen doped iridium layer and forming a ferroelectric dielectric layer thereover. During the formation of the ferroelectric, the oxygen doped iridium layer converts to an iridium oxide layer.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括在形成电容器的铁电介质部分期间降低底部电极材料的减少。该方法包括形成氧掺杂铱层并在其上形成铁电介质层。在形成铁电体期间，掺杂氧的铱层转化为氧化铱层。

54. 发明授权

US06555431B1 Method for forming integrated circuit capacitor and memory 有权
标题翻译：用于形成集成电路电容器和存储器的方法
公开(公告)号：US06555431B1
公开(公告)日：2003-04-29
申请号：US09712774
申请日：2000-11-16
申请人： Guoqiang Xing , Scott R. Summerfelt , Rajesh Khamankar
发明人： Guoqiang Xing , Scott R. Summerfelt , Rajesh Khamankar
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/32136 , H01L21/32139 , H01L28/55 , H01L28/60
摘要： A method for etching a feature in a platinum layer 834 overlying a second material 818 without substantially etching the second material. The method includes the the steps of: forming an adhesion-promoting layer 824 between the platinum layer and the second material; forming a hardmask layer 829 over the platinum layer; patterning and etching the hardmask layer in accordance with desired dimensions of the feature; and etching portions of the platinum layer not covered by the hardmask layer 832, the etching stopping on the adhesion-promoting layer. In further embodiments the adhesion-promoting and hardmask layers are Ti—Al—N including at least 1% of aluminum.
摘要翻译：一种用于蚀刻铂层834中覆盖第二材料818而不基本上蚀刻第二材料的特征的方法。该方法包括以下步骤：在铂层和第二材料之间形成粘合促进层824; 在铂层上形成硬掩模层829; 根据特征的期望尺寸对硬掩模层进行图案化和蚀刻; 并且蚀刻未被硬掩模层832覆盖的铂层的部分，蚀刻停止在粘合促进层上。在另外的实施方案中，粘合促进和硬掩模层是包括至少1％的铝的Ti-Al-N。

55. 发明授权

US06432473B1 PB substituted perovskites for thin films dielectrics 失效
标题翻译： PB取代的钙钛矿用于薄膜电介质
公开(公告)号：US06432473B1
公开(公告)日：2002-08-13
申请号：US08458999
申请日：1995-06-01
申请人： Scott R. Summerfelt , Howard R. Beratan , Bernard M. Kulwicki
发明人： Scott R. Summerfelt , Howard R. Beratan , Bernard M. Kulwicki
IPC分类号： B05D512
CPC分类号： H01L27/11502 , H01G4/1227 , H01L21/02197 , H01L21/31691
摘要： The invention described is a method of forming an improved dielectric material by adding lead to an original perovskite material having an original critical grain size to form a lead enhanced perovskite material, then forming a layer of the lead enhanced perovskite material having an average grain size less than the original critical grain size whereby the dielectric constant of the layer is substantially greater than the dielectric constant of the original perovskite material with an average grain size similar to the average grain size of the layer. The critical grain size, as used herein, means the largest grain size such that the dielectric constant starts to rapidly decrease with decreasing grain sizes. Preferably, the lead enhanced perovskite material is further doped with one or more acceptor dopants whereby the resistivity is substantially increased and/or the loss tangent is substantially decreased. Preferably, the original perovskite material has a chemical composition ABO3, where A is one or more monovalent, divalent or trivalent elements, and B is one or more pentavalent, tetravalent, trivalent or divalent elements.
摘要翻译：本发明描述了一种通过将铅添加到具有原始临界晶粒尺寸的原始钙钛矿材料以形成铅增强的钙钛矿材料形成改进的介电材料的方法，然后形成平均晶粒尺寸较小的铅增强的钙钛矿材料层比原始的临界晶粒大小，由此该层的介电常数基本上大于原始钙钛矿材料的介电常数，平均晶粒尺寸与层的平均晶粒尺寸相似。如本文所用，临界晶粒尺寸是指最大的晶粒尺寸，使得随着晶粒尺寸的减小，介电常数开始迅速降低。优选地，铅增强的钙钛矿材料进一步掺杂有一种或多种受体掺杂剂，由此电阻率显着增加和/或损耗角正切减小。优选地，原始钙钛矿材料具有化学组成ABO 3，其中A是一个或多个一价，二价或三价元素，B是一种或多种五价，四价，三价或二价元素。

56. 发明授权

US06211035B1 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06211035B1
公开(公告)日：2001-04-03
申请号：US09392988
申请日：1999-09-09
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L2120
CPC分类号： H01L27/11502 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

57. 发明授权

US06204069B1 Lightly donor doped electrodes for high-dielectric-constant materials 失效
公开(公告)号：US06204069B1
公开(公告)日：2001-03-20
申请号：US08317108
申请日：1994-10-03
申请人： Scott R. Summerfelt , Howard R. Beratan , Bruce Gnade
发明人： Scott R. Summerfelt , Howard R. Beratan , Bruce Gnade
IPC分类号： H01L2100
CPC分类号： H01G4/008 , H01L21/31691 , H01L27/11502 , H01L28/56 , Y10S257/917 , Y10T29/43 , Y10T29/435
摘要： A preferred embodiment of this invention comprises a conductive lightly donor doped perovskite layer (e.g. lightly La doped BST 34), and a high-dielectric-constant material layer (e.g. undoped BST 36) overlaying the conductive lightly donor doped perovskite layer. The conductive lightly donor doped perovskite layer provides a substantially chemically and structurally stable electrical connection to the high-dielectric-constant material layer. A lightly donor doped perovskite generally has much less resistance than undoped, acceptor doped, or heavily donor doped HDC materials. The amount of donor doping to make the material conductive (or resistive) is normally dependent on the process conditions (e.g. temperature, atmosphere, grain size, film thickness and composition). This resistivity may be further decreased if the perovskite is exposed to reducing conditions. The lightly donor doped perovskite can be deposited and etched by effectively the same techniques that are developed for the high-dielectric-constant material. The same equipment may used to deposit and etch both the perovskite electrode and the dielectric. These structures may also be used for multilayer capacitors and other thin-film ferroelectric devices such as pyroelectric materials, non-volatile memories, thin-film piezoelectric and thin-film electro-optic oxides.

58. 发明授权

US6117689A Stable high-dielectric-constant material electrode and method 有权
标题翻译：稳定的高介电常数材料电极及方法
公开(公告)号：US6117689A
公开(公告)日：2000-09-12
申请号：US217758
申请日：1998-12-21
申请人： Scott R. Summerfelt
发明人： Scott R. Summerfelt
IPC分类号： H01L21/02 , H01L21/3205 , H01L21/70
CPC分类号： H01L28/60 , H01L21/32051
摘要： A structure for, and method of forming, an oxygen diffusion resistant electrode for high-dielectric-constant materials is disclosed. The electrode comprises a single grain of an oxygen stable material over a barrier layer. The single crystal oxygen stable layer is generally substantially impervious to oxygen diffusion at all relevant deposition and annealing temperatures. The disclosed structure is an integrated circuit comprising an array of microelectronic structures, with each of the microelectronic structures comprising an oxidizable layer (e.g., polysilicon 50), a barrier layer (e.g. TiN 64) overlying the oxidizable layer, a single crystal oxygen stable layer (e.g., Pt 98) overlying the barrier layer, and a high-dielectric-constant material layer (e.g., barium strontium titanate 36) overlying the oxygen stable layer. The disclosed method of fabricating an integrated circuit comprises forming an array of microelectronic structures, wherein forming each of said microelectronic structures comprises forming a barrier layer on an oxidizable layer, depositing a single crystal oxygen stable layer on the barrier layer, and depositing a high-dielectric-constant material layer on the oxygen stable layer. The single crystal oxygen stable layer prevents oxidation of the barrier layer and the oxidizable layer during subsequent processing.
摘要翻译：公开了用于高介电常数材料的氧扩散阻止电极的结构和形成方法。电极在阻挡层上包括单一的氧稳定材料晶粒。在所有相关沉积和退火温度下，单晶氧稳定层通常基本上不渗透氧气扩散。所公开的结构是包括微电子结构阵列的集成电路，其中每个微电子结构包括可氧化层（例如，多晶硅50），覆盖在可氧化层上的阻挡层（例如TiN 64），单晶氧稳定层（例如Pt 98）和覆盖在氧稳定层上的高介电常数材料层（例如，钛酸钡锶36）。所公开的制造集成电路的方法包括形成微电子结构的阵列，其中形成每个所述微电子结构包括在可氧化层上形成阻挡层，在阻挡层上沉积单晶氧稳定层，氧稳定层上的介电常数材料层。单晶氧稳定层防止在后续处理期间阻挡层和可氧化层的氧化。

59. 发明授权

US6100200A Sputtering process for the conformal deposition of a metallization or insulating layer 失效
标题翻译：用于金属化或绝缘层的共形沉积的溅射工艺
公开(公告)号：US6100200A
公开(公告)日：2000-08-08
申请号：US218563
申请日：1998-12-21
申请人： Peter C. Van Buskirk , Michael W. Russell , Daniel J. Vestyck , Scott R. Summerfelt , Theodore S. Moise
发明人： Peter C. Van Buskirk , Michael W. Russell , Daniel J. Vestyck , Scott R. Summerfelt , Theodore S. Moise
IPC分类号： C23C14/04 , C23C14/34 , H01L21/02 , H01L21/285 , H01L21/768 , H01L21/311
CPC分类号： H01L28/55 , C23C14/046 , C23C14/34 , H01L21/76877 , H01L21/76895 , H01L21/2855
摘要： The present invention is a method related to the deposition of a metallization layer in a trench in a semiconductor substrate. The focus of the invention is to sequentially perform heated deposition and etch unit processes to provide a good conformal film of metal on the inner surfaces of a via or trench. The deposition and etch steps can also be performed simultaneously.
摘要翻译：本发明是涉及在半导体衬底中的沟槽中沉积金属化层的方法。本发明的重点是依次执行加热沉积和蚀刻单元工艺以在通孔或沟槽的内表面上提供良好的金属保形膜。沉积和蚀刻步骤也可以同时进行。

60. 发明授权

US6083812A Heteroepitaxy by large surface steps 失效
标题翻译：通过大面积台阶进行异质外延
公开(公告)号：US6083812A
公开(公告)日：2000-07-04
申请号：US12556
申请日：1993-02-02
申请人： Scott R. Summerfelt
发明人： Scott R. Summerfelt
IPC分类号： C30B25/18 , C30B33/06 , H01L21/04 , H01L21/20 , H01L21/205 , H01L21/34
CPC分类号： H01L29/66969 , H01L21/02378 , H01L21/0242 , H01L21/0243 , H01L21/02433 , H01L21/02458 , H01L21/02529 , H01L21/0254 , H01L21/0262 , H01L21/02658 , H01L21/0445 , Y10S438/931
摘要： A method for heteroepitaxial growth and the device wherein a single crystal ceramic substrate, preferably Y stabilized zirconia, MgAl.sub.2 O.sub.4, A1.sub.2 O.sub.3, 3C--SiC, 6H--SiC or MgO is cut and polished at from about 1.0 to about 10 degrees off axis to produce a substantially flat surface. The atoms on the surface are redistributed on the surface to produce surface steps of at least three lattice spacings. An optional epitaxially grown ceramic buffer layer, preferably AlN or GaN, is then formed on the substrate. Then a layer of semiconductor, preferably SiC, AlN when the buffer layer is used and is not AlN or GaN is grown over the substrate and buffer layer, if used.
摘要翻译：用于异质外延生长的方法和其中将单晶陶瓷衬底，优选Y稳定的氧化锆，MgAl 2 O 4，A 12 O 3，3C-SiC，6H-SiC或MgO在离轴上约1.0至约10度切割和抛光的装置，以产生基本平坦的表面。表面上的原子重新分布在表面上以产生至少三个晶格间距的表面步骤。然后在衬底上形成任选的外延生长的陶瓷缓冲层，优选AlN或GaN。然后，如果使用缓冲层，并且不是AlN或GaN，则半导体层，优选SiC，AlN生长在衬底和缓冲层上。

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