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41. 发明授权

US08252644B2 Method for forming a nonvolatile memory cell comprising a reduced height vertical diode 有权
标题翻译：用于形成包括减小的高度立方二极管的非易失性存储单元的方法
公开(公告)号：US08252644B2
公开(公告)日：2012-08-28
申请号：US13228109
申请日：2011-09-08
申请人： Scott Brad Herner , Steven J. Radigan
发明人： Scott Brad Herner , Steven J. Radigan
IPC分类号： H01L29/80
CPC分类号： G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0649 , H01L29/66272 , H01L29/732 , H01L29/868
摘要： A method for forming a nonvolatile memory cell is provided that includes: (1) forming a rail-shaped first conductor above a substrate, (2) forming a rail-shaped second conductor above the first conductor, and (3) forming a substantially vertical first pillar disposed between the first conductor and the second conductor. The first pillar includes a vertically oriented p-i-n diode, and the p-i-n diode includes: (a) a bottom heavily doped region having a first conductivity type, (b) a middle intrinsic or lightly doped region, and (c) a top heavily doped region having a second conductivity type opposite the first conductivity type. The bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF2 ions. Numerous additional aspects are provided.
摘要翻译：提供了一种用于形成非易失性存储单元的方法，其包括：（1）在基板上形成轨道状的第一导体，（2）在第一导体的上方形成轨道状的第二导体，以及（3）第一支柱设置在第一导体和第二导体之间。第一柱包括垂直定向的pin二极管，并且pin二极管包括：（a）具有第一导电类型的底部重掺杂区域，（b）中间固有或轻掺杂区域，以及（c）顶部重掺杂区域具有与第一导电类型相反的第二导电类型。通过注入砷离子来掺杂底部重掺杂区，通过注入BF 2离子来掺杂顶部重掺杂区。还提供了许多其他方面。

42. 发明授权

US07994068B2 Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon 有权
标题翻译：使用无定形碳上的氮氧化硅硬掩模制造3-D集成电路的方法
公开(公告)号：US07994068B2
公开(公告)日：2011-08-09
申请号：US12750596
申请日：2010-03-30
申请人： Steven J. Radigan , Michael W. Konevecki
发明人： Steven J. Radigan , Michael W. Konevecki
IPC分类号： H01L21/31
CPC分类号： H01L27/1021 , H01L23/5252 , H01L27/0688 , H01L29/8615 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.
摘要翻译：一种用于制造3-D单片存储器件的方法。无定形碳上的氮氧化硅（SixOyNz）被用于对硅，氧化物和钨具有高选择性的有效的，容易移除的硬掩模。使用光致抗蚀剂层蚀刻硅 - 氧氮化物层，并且使用所得到的蚀刻的六方氮化物层来蚀刻无定形碳层。使用无定形碳层蚀刻硅，氧化物和/或钨层。在一个实施方案中，通过使用图案化的非晶碳层作为硬掩模来蚀刻诸如二氧化硅（SiO 2）的氧化物层来形成3-D单片存储器件的导电轨道。通过使用另一图案化的非晶碳层作为硬掩模蚀刻多晶硅层，在导电轨道之间的多晶硅中形成存储单元二极管。与构建3-D单片存储器件类似地形成附加电平的导电轨和存储单元二极管。

43. 发明申请

US20100184259A1 METHOD FOR FABRICATING A 3-D INTEGRATED CIRCUIT USING A HARD MASK OF SILICON-OXYNITRIDE ON AMORPHOUS CARBON 有权
标题翻译：使用硅氧烷在非晶碳上的硬掩模制造三维集成电路的方法
公开(公告)号：US20100184259A1
公开(公告)日：2010-07-22
申请号：US12750596
申请日：2010-03-30
申请人： Steven J. Radigan , Michael W. Konevecki
发明人： Steven J. Radigan , Michael W. Konevecki
IPC分类号： H01L21/822
CPC分类号： H01L27/1021 , H01L23/5252 , H01L27/0688 , H01L29/8615 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.
摘要翻译：一种用于制造3-D单片存储器件的方法。无定形碳上的氮氧化硅（SixOyNz）被用于对硅，氧化物和钨具有高选择性的有效的，容易移除的硬掩模。使用光致抗蚀剂层蚀刻硅 - 氧氮化物层，并且使用所得到的蚀刻的六方氮化物层来蚀刻无定形碳层。使用无定形碳层蚀刻硅，氧化物和/或钨层。在一个实施方案中，通过使用图案化的非晶碳层作为硬掩模来蚀刻诸如二氧化硅（SiO 2）的氧化物层来形成3-D单片存储器件的导电轨道。通过使用另一图案化的非晶碳层作为硬掩模蚀刻多晶硅层，在导电轨道之间的多晶硅中形成存储单元二极管。与构建3-D单片存储器件类似地形成附加电平的导电轨和存储单元二极管。

44. 发明申请

US20100181657A1 NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE 有权
标题翻译：包含降低高度垂直二极管的非易失性存储单元
公开(公告)号：US20100181657A1
公开(公告)日：2010-07-22
申请号：US12481684
申请日：2009-06-10
申请人： S. Brad Herner , Steven J. Radigan
发明人： S. Brad Herner , Steven J. Radigan
IPC分类号： H01L29/868 , H01L21/425
CPC分类号： G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0649 , H01L29/66272 , H01L29/732 , H01L29/868
摘要： A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided.
摘要翻译：非易失性存储单元包括：形成在衬底上方的第一高度处的轨道状第一导体; 形成在第一导体上方的轨道形状的第二导体; 以及包括p-i-n第一二极管的垂直取向的第一柱; 其中所述第一柱设置在所述第二导体和所述第一导体之间; 其中所述第一二极管包括固有或轻掺杂区域; 并且其中所述固有或轻掺杂区域具有约300埃或更大的第一厚度。还提供了许多其他方面。

45. 发明申请

US20090155962A1 Method for fabricating pitch-doubling pillar structures 有权
标题翻译：制造俯仰倍增柱结构的方法
公开(公告)号：US20090155962A1
公开(公告)日：2009-06-18
申请号：US12000758
申请日：2007-12-17
申请人： Christopher J. Petti , Steven J. Radigan
发明人： Christopher J. Petti , Steven J. Radigan
IPC分类号： H01L21/82
CPC分类号： H01L27/102 , H01L21/0337
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔开的特征，在所述至少两个特征上形成侧壁间隔物，填充第一侧壁第一特征上的间隔物和具有填充物特征的第二特征上的第二侧壁间隔物，选择性地移除侧壁间隔物以留下第一特征，填料特征和第二特征彼此间隔开，并且蚀刻至少一个装置层，使用第一特征，填充特征和第二特征作为掩模。

46. 发明授权

US07285464B2 Nonvolatile memory cell comprising a reduced height vertical diode 有权
标题翻译：非易失性存储单元包括减小的高度的垂直二极管
公开(公告)号：US07285464B2
公开(公告)日：2007-10-23
申请号：US11015824
申请日：2004-12-17
申请人： S. Brad Herner , Steven J. Radigan
发明人： S. Brad Herner , Steven J. Radigan
IPC分类号： H01L21/336
CPC分类号： G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0649 , H01L29/66272 , H01L29/732 , H01L29/868
摘要： A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.
摘要翻译：根据本发明的非易失性存储单元包括底部导体，半导体柱和顶部导体。半导体柱包括结二极管，其包括底部重掺杂区域，中间固有或轻掺杂区域和顶部重掺杂区域，其中顶部和底部重掺杂区域的导电类型相反。结二极管是垂直取向的，并且具有降低的高度，在约500埃至约3500埃之间。可以形成这样的单元的单片三维存储器阵列，其包括多个存储器级，电平彼此整体地形成。

47. 发明申请

US20110318911A1 NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE 有权
标题翻译：包含降低高度垂直二极管的非易失性存储单元
公开(公告)号：US20110318911A1
公开(公告)日：2011-12-29
申请号：US13228109
申请日：2011-09-08
申请人： S. Brad Herner , Steven J. Radigan
发明人： S. Brad Herner , Steven J. Radigan
IPC分类号： H01L21/8229 , H01L21/329
CPC分类号： G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0649 , H01L29/66272 , H01L29/732 , H01L29/868
摘要： A method for forming a nonvolatile memory cell is provided that includes: (1) forming a rail-shaped first conductor above a substrate, (2) forming a rail-shaped second conductor above the first conductor, and (3) forming a substantially vertical first pillar disposed between the first conductor and the second conductor. The first pillar includes a vertically oriented p-i-n diode, and the p-i-n diode includes: (a) a bottom heavily doped region having a first conductivity type, (b) a middle intrinsic or lightly doped region, and (c) a top heavily doped region having a second conductivity type opposite the first conductivity type. The bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF2 ions. Numerous additional aspects are provided.
摘要翻译：提供了一种用于形成非易失性存储单元的方法，其包括：（1）在基板上形成轨道状的第一导体，（2）在第一导体的上方形成轨道状的第二导体，以及（3）第一支柱设置在第一导体和第二导体之间。第一柱包括垂直定向的pin二极管，并且pin二极管包括：（a）具有第一导电类型的底部重掺杂区域，（b）中间固有或轻掺杂区域，以及（c）顶部重掺杂区域具有与第一导电类型相反的第二导电类型。通过注入砷离子来掺杂底部重掺杂区，通过注入BF 2离子来掺杂顶部重掺杂区。还提供了许多其他方面。

48. 发明申请

US20110014779A1 Method of making damascene diodes using sacrificial material 有权
公开(公告)号：US20110014779A1
公开(公告)日：2011-01-20
申请号：US12458543
申请日：2009-07-15
申请人： Raghuveer S. Makala , Vance Dunton , Yoichiro Tanaka , Steven Maxwell , Tong Zhang , Steven J. Radigan
发明人： Raghuveer S. Makala , Vance Dunton , Yoichiro Tanaka , Steven Maxwell , Tong Zhang , Steven J. Radigan
IPC分类号： H01L21/20
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.

49. 发明授权

US07718546B2 Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon 有权
标题翻译：使用无定形碳上的氮氧化硅硬掩模制造3-D集成电路的方法
公开(公告)号：US07718546B2
公开(公告)日：2010-05-18
申请号：US11769027
申请日：2007-06-27
申请人： Steven J. Radigan , Michael W. Konevecki
发明人： Steven J. Radigan , Michael W. Konevecki
IPC分类号： H01L21/469
CPC分类号： H01L27/1021 , H01L23/5252 , H01L27/0688 , H01L29/8615 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.
摘要翻译：一种用于制造3-D单片存储器件的方法。无定形碳上的氮氧化硅（SixOyNz）被用于对硅，氧化物和钨具有高选择性的有效的，容易移除的硬掩模。使用光致抗蚀剂层蚀刻硅 - 氧氮化物层，并且使用所得到的蚀刻的六方氮化物层来蚀刻无定形碳层。使用无定形碳层蚀刻硅，氧化物和/或钨层。在一个实施方案中，通过使用图案化的非晶碳层作为硬掩模来蚀刻诸如二氧化硅（SiO 2）的氧化物层来形成3-D单片存储器件的导电轨道。通过使用另一图案化的非晶碳层作为硬掩模蚀刻多晶硅层，在导电轨道之间的多晶硅中形成存储单元二极管。与构建3-D单片存储器件类似地形成附加电平的导电轨和存储单元二极管。

50. 发明申请

US20090273022A1 CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH 审中-公开
标题翻译：导电硬掩模，以保护在TRENCH ETCH期间的图案特征
公开(公告)号：US20090273022A1
公开(公告)日：2009-11-05
申请号：US12502796
申请日：2009-07-14
申请人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
发明人： Steven J. Radigan , Usha Raghuram , Samuel V. Dunton , Michael W. Konevecki
IPC分类号： H01L27/105 , H01L21/8234 , H01L21/822 , H01L27/06
CPC分类号： H01L23/5252 , H01L27/1021 , H01L29/6609 , H01L2924/0002 , H01L2924/00
摘要： A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, iii) depositing a first dielectric layer above the first pillars, and iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, the lowest point in the trenches is above the lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride. The method also includes monolithically forming a second memory level above the first memory level. Other aspects are also described.
摘要翻译：单片三维存储器阵列通过一种方法形成，该方法包括通过在第一方向上形成多个沿第一方向延伸的多个第一基本上平行的导体形成第一存储器电平，ii）在第一导体上方形成第一柱，柱，其包括在垂直取向的二极管上方的第一导电层或层堆叠，在单个光刻步骤中形成的第一柱，iii）在第一柱上方沉积第一电介质层，以及iv）在第一栅极中蚀刻多个基本上平行的第一沟槽所述第一沟槽在第二方向上延伸，其中在所述蚀刻步骤之后，所述沟槽中的最低点高于所述第一导电层或层堆叠的最低点，其中所述第一导电层或所述层堆叠不包含电阻率开关金属氧化物或氮化物。该方法还包括在第一存储器级上方单片地形成第二存储器级。还描述了其他方面。

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