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1. 发明授权

US08252644B2 Method for forming a nonvolatile memory cell comprising a reduced height vertical diode 有权
标题翻译：用于形成包括减小的高度立方二极管的非易失性存储单元的方法
公开(公告)号：US08252644B2
公开(公告)日：2012-08-28
申请号：US13228109
申请日：2011-09-08
申请人： Scott Brad Herner , Steven J. Radigan
发明人： Scott Brad Herner , Steven J. Radigan
IPC分类号： H01L29/80
CPC分类号： G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0649 , H01L29/66272 , H01L29/732 , H01L29/868
摘要： A method for forming a nonvolatile memory cell is provided that includes: (1) forming a rail-shaped first conductor above a substrate, (2) forming a rail-shaped second conductor above the first conductor, and (3) forming a substantially vertical first pillar disposed between the first conductor and the second conductor. The first pillar includes a vertically oriented p-i-n diode, and the p-i-n diode includes: (a) a bottom heavily doped region having a first conductivity type, (b) a middle intrinsic or lightly doped region, and (c) a top heavily doped region having a second conductivity type opposite the first conductivity type. The bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF2 ions. Numerous additional aspects are provided.
摘要翻译：提供了一种用于形成非易失性存储单元的方法，其包括：（1）在基板上形成轨道状的第一导体，（2）在第一导体的上方形成轨道状的第二导体，以及（3）第一支柱设置在第一导体和第二导体之间。第一柱包括垂直定向的pin二极管，并且pin二极管包括：（a）具有第一导电类型的底部重掺杂区域，（b）中间固有或轻掺杂区域，以及（c）顶部重掺杂区域具有与第一导电类型相反的第二导电类型。通过注入砷离子来掺杂底部重掺杂区，通过注入BF 2离子来掺杂顶部重掺杂区。还提供了许多其他方面。

2. 发明授权

US11183534B2 Light emitting device with small footprint 有权
公开(公告)号：US11183534B2
公开(公告)日：2021-11-23
申请号：US16835614
申请日：2020-03-31
申请人： Scott Brad Herner
发明人： Scott Brad Herner
IPC分类号： H01L27/15 , H01L25/16 , H01L33/50 , H01L33/10
摘要： This application describes a light emitting device or an assembly of light emitting devices, each with a small footprint. The light emitting device comprises two transistors, a capacitor, and an LED. The transistors comprise single crystal semiconductor. The capacitor is vertically-oriented. The LED overlies the transistors and capacitor. Methods to form the light emitting device or assembly are discussed.

3. 发明申请

US20210305464A1 Light emitting device with small footprint 有权
公开(公告)号：US20210305464A1
公开(公告)日：2021-09-30
申请号：US16835614
申请日：2020-03-31
申请人： Scott Brad Herner
发明人： Scott Brad Herner
IPC分类号： H01L33/48 , H01L33/10 , H01L33/50 , H01L49/02
摘要： This application describes a light emitting device or an assembly of light emitting devices, each with a small footprint. The light emitting device comprises two transistors, a capacitor, and an LED. The transistors comprise single crystal semiconductor. The capacitor is vertically-oriented. The LED overlies the transistors and capacitor. Methods to form the light emitting device or assembly are discussed.

4. 发明申请

US20210134774A1 Area-efficient subpixel apparatus 有权
公开(公告)号：US20210134774A1
公开(公告)日：2021-05-06
申请号：US16671075
申请日：2019-10-31
申请人： Scott Brad Herner
发明人： Scott Brad Herner
IPC分类号： H01L25/16
摘要： This application describes a subpixel apparatus comprising two transistors, a capacitor, and a small LED. The transistors and capacitor are fabricated in such a manner as to occupy a reduced area and have the small LED overlie them. Methods to form the subpixel apparatus are discussed.

5. 发明授权

US10566317B2 Light emitting device with small size and large density 有权
公开(公告)号：US10566317B2
公开(公告)日：2020-02-18
申请号：US15984370
申请日：2018-05-20
申请人： Scott Brad Herner
发明人： Scott Brad Herner
IPC分类号： H01L25/075 , H01L23/48 , H01L33/30 , H01L33/32 , H01L33/42 , H01L33/50 , H01L33/60 , H01L33/62 , H01L21/285 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L29/45 , H01L33/22
摘要： This application describes a light emitting device, an assembly of light emitting devices, a display comprising assemblies of light emitting devices, and methods of fabricating same. The light emitting device comprises a transistor, an LED that at least partially overlies the transistor, a reflector layer disposed between the LED and transistor, and conductive wires that connect electrically the transistor to the LED. The assembly comprises a plurality of light emitting devices, and the display comprises a plurality of assemblies.

6. 发明授权

US09252191B2 Seed layer for a p+ silicon germanium material for a non-volatile memory device and method 有权
标题翻译：用于非易失性存储器件的p +硅锗材料的种子层和方法
公开(公告)号：US09252191B2
公开(公告)日：2016-02-02
申请号：US13189401
申请日：2011-07-22
申请人： Mark Harold Clark , Scott Brad Herner
发明人： Mark Harold Clark , Scott Brad Herner
IPC分类号： H01L21/02 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2463 , H01L21/02532 , H01L21/0262 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/148 , H01L45/16 , H01L45/1616 , H01L45/1675
摘要： A method of forming a non-volatile memory device includes providing a substrate having a surface, depositing a dielectric overlying the surface, forming a first wiring structure overlying the dielectric, depositing silicon material overlying the first wiring structure, the silicon layer having a thickness of less than about 100 Angstroms, depositing silicon germanium material at a temperature raging from about 400 to about 490 Degrees Celsius overlying the first wiring structure using the silicon layer as a seed layer, wherein the silicon germanium material is substantially free of voids and has polycrystalline characteristics, depositing resistive switching material (e.g. amorphous silicon material) overlying the silicon germanium material, depositing a conductive material overlying the resistive material, and forming a second wiring structure overlying the conductive material.
摘要翻译：一种形成非易失性存储器件的方法包括提供具有表面的衬底，沉积覆盖在表面上的电介质，形成覆盖电介质的第一布线结构，沉积覆盖第一布线结构的硅材料，硅层的厚度小于约100埃，使用硅层作为种子层，以大约400至大约490摄氏度的温度沉积硅锗材料，其中硅锗材料基本上没有空隙并具有多晶特性沉积覆盖硅锗材料的电阻开关材料（例如非晶硅材料），沉积覆盖电阻材料的导电材料，以及形成覆盖导电材料的第二布线结构。

7. 发明授权

US08815696B1 Disturb-resistant non-volatile memory device using via-fill and etchback technique 有权
标题翻译：使用通孔填充和回蚀技术的抗干扰非易失性存储器件
公开(公告)号：US08815696B1
公开(公告)日：2014-08-26
申请号：US13339939
申请日：2011-12-29
申请人： Scott Brad Herner
发明人： Scott Brad Herner
IPC分类号： H01L21/20
CPC分类号： H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/148 , H01L45/16 , H01L45/1683
摘要： A method of forming a disturb-resistant non volatile memory device includes providing a substrate and forming a first dielectric thereon, forming a first strip of material separated from a second strip of material from a first wiring material, and forming a second dielectric thereon to fill a gap between the first and second strips of material. Openings are formed in the second dielectric exposing portions of the first wiring material. Filing the openings by p+ polysilicon contact material, and then an undoped amorphous silicon material, and then a metal material. A second wiring structure is formed thereon to contact the metal material in the openings. Resistive switching cells are formed from the first wiring structure, the second wiring structure, the contact material, the undoped amorphous silicon material, and the metal material.
摘要翻译：形成抗干扰非易失性存储器件的方法包括提供衬底并在其上形成第一电介质，形成与第一条布料材料分离的第一条材料的第一条材料，并在其上形成第二电介质以填充第一和第二条材料之间的间隙。开口形成在第一布线材料的第二电介质曝光部分中。通过p +多晶硅接触材料填充开口，然后加入未掺杂的非晶硅材料，再用金属材料。在其上形成第二布线结构以与开口中的金属材料接触。电阻式开关电池由第一布线结构，第二布线结构，接触材料，未掺杂的非晶硅材料和金属材料形成。

8. 发明授权

US08592792B2 Heterojunction device comprising a semiconductor oxide and a resistivity-switching oxide or nitride 有权
标题翻译：异质结装置包括半导体氧化物和电阻率切换氧化物或氮化物
公开(公告)号：US08592792B2
公开(公告)日：2013-11-26
申请号：US13553963
申请日：2012-07-20
申请人： Tanmay Kumar , Scott Brad Herner
发明人： Tanmay Kumar , Scott Brad Herner
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： H01L29/868 , H01L21/84 , H01L27/1021 , H01L27/2409 , H01L29/165 , H01L29/22 , H01L29/267 , H01L29/417 , H01L29/737 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A monolithic three dimensional memory array is provided that includes a first memory level formed above a substrate, and a second memory level monolithically formed above the first memory level. The first memory level includes a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction, a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction, the second direction different from the first direction, the second conductors above the first conductors, and a first plurality of devices. Each of the first plurality of devices is disposed between one of the first conductors and one of the second conductors, and includes a resistivity-switching binary metal oxide or nitride compound and a silicon, germanium, or silicon-germanium alloy resistor of a single conductivity type. Numerous other aspects are provided.
摘要翻译：提供了一种单片三维存储器阵列，其包括形成在衬底上方的第一存储器级和在第一存储器级上方单片地形成的第二存储器级。第一存储器级包括在第一方向上延伸的第一多个基本上平行的基本上共面的导体，在第二方向上延伸的第二多个大致平行的基本上共面的导体，第二方向不同于第一方向，第二方向与第一方向不同第一导体和第一多个装置。第一多个器件中的每一个设置在第一导体中的一个和第二导体中的一个之间，并且包括电阻率切换二元金属氧化物或氮化物化合物以及具有单一导电性的硅，锗或硅 - 锗合金电阻器类型。提供了许多其他方面。

9. 发明授权

US08519485B2 Pillar structure for memory device and method 有权
公开(公告)号：US08519485B2
公开(公告)日：2013-08-27
申请号：US13465188
申请日：2012-05-07
申请人： Scott Brad Herner
发明人： Scott Brad Herner
IPC分类号： H01L29/02 , H01L29/80 , H01L29/76
CPC分类号： H01L45/1675 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/148 , H01L45/1608 , H01L45/1616 , H01L45/1666
摘要： A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

10. 发明授权

US08349664B2 Nonvolatile memory cell comprising a diode and a resistance-switching material 有权
标题翻译：包括二极管和电阻切换材料的非易失性存储单元
公开(公告)号：US08349664B2
公开(公告)日：2013-01-08
申请号：US12855462
申请日：2010-08-12
申请人： Scott Brad Herner , Christopher J. Petti , Tanmay Kumar
发明人： Scott Brad Herner , Christopher J. Petti , Tanmay Kumar
IPC分类号： H01L21/82
CPC分类号： H01L27/249 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HfxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.
摘要翻译：在形成在衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选为金属氧化物或氮化物，例如NixOy，NbxOy，TixOy，HfxOy，AlxOy，MgxOy，CoxOy，CrxOy ，VxOy，ZnxOy，ZrxOy，BxNy和AlxNy。在优选实施例中，二极管形成为设置在导体之间的垂直支柱。可以堆叠多个存储器级别以形成单片三维存储器阵列。在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

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