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41. 发明授权

US07151315B2 Method of a non-metal barrier copper damascene integration 有权
标题翻译：非金属阻挡铜大马士革一体化方法
公开(公告)号：US07151315B2
公开(公告)日：2006-12-19
申请号：US10459222
申请日：2003-06-11
申请人： Zhen-Cheng Wu , Yung-Chen Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Yung-Chen Lu , Syun-Ming Jang
IPC分类号： H01L23/50
CPC分类号： H01L21/76802 , H01L21/76831 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method, integrated circuit, and interconnect structure utilizing non-metal barrier copper damascene integration. The method is provided for fabricating an interconnect for connecting to one or more front end of line (FEOL) devices. The method includes forming a layer of doped oxide on the one or more FEOL devices and forming a first barrier layer on the layer of doped oxide, the first barrier layer comprising such material as silicon oxycarbide (SiOC) or silicon carbonitride (SiCN). The method further includes forming a plurality of refractory metal plugs in the first barrier layer and the doped oxide layer, forming a low dielectric constant film over the first barrier layer and the plurality of refractory metal plugs, and performing a first etch to create trenches through the low dielectric constant film. The plurality of refractory metal plugs and the first barrier layer perform as an etch-stop.
摘要翻译：本公开提供了利用非金属阻挡铜镶嵌一体化的方法，集成电路和互连结构。该方法用于制造用于连接到一个或多个前端（FEOL）装置的互连件。该方法包括在一个或多个FEOL器件上形成掺杂氧化物层，并在掺杂氧化物层上形成第一势垒层，第一势垒层包含碳氧化硅（SiOC）或碳氮化硅（SiCN）等材料。该方法还包括在第一阻挡层和掺杂氧化物层中形成多个难熔金属塞，在第一阻挡层和多个耐火金属插塞上形成低介电常数膜，并进行第一蚀刻以产生沟槽低介电常数膜。多个难熔金属插塞和第一阻挡层执行蚀刻停止。

42. 发明申请

US20060154481A1 Decreasing Metal-Silicide Oxidation During Wafer Queue Time 有权
标题翻译：在晶片队列时间内减少金属硅化物氧化
公开(公告)号：US20060154481A1
公开(公告)日：2006-07-13
申请号：US10905517
申请日：2005-01-07
申请人： Zhen-Cheng Wu , Cheng-Hung Chang , Yu-Lien Huang , Shwang-Ming Cheng
发明人： Zhen-Cheng Wu , Cheng-Hung Chang , Yu-Lien Huang , Shwang-Ming Cheng
IPC分类号： H01L21/44
CPC分类号： H01L21/76888 , H01L21/3003 , H01L29/665
摘要： Disclosed herein are various embodiments of semiconductor devices and related methods of manufacturing a semiconductor device. In one embodiment, a method includes providing a semiconductor substrate and forming a metal silicide on the semiconductor substrate. In addition, the method includes treating an exposed surface of the metal silicide with a hydrogen/nitrogen-containing compound to form a treated layer on the exposed surface, where the composition of the treated layer hinders oxidation of the exposed surface. The method may then further include depositing a dielectric layer over the treated layer and the exposed surface of the metal silicide.
摘要翻译：这里公开了半导体器件的各种实施例和制造半导体器件的相关方法。在一个实施例中，一种方法包括提供半导体衬底并在半导体衬底上形成金属硅化物。此外，该方法包括用含氢/氮化合物处理金属硅化物的暴露表面以在暴露表面上形成处理层，其中处理层的组成阻碍了暴露表面的氧化。该方法可以进一步包括在经处理的层和金属硅化物的暴露表面上沉积介电层。

43. 发明申请

US20060134906A1 Post-ESL porogen burn-out for copper ELK integration 有权
标题翻译：用于铜ELK整合的后ESL致孔剂烧尽
公开(公告)号：US20060134906A1
公开(公告)日：2006-06-22
申请号：US11020372
申请日：2004-12-22
申请人： Yung-Cheng Lu , Ying-Tsung Chen , Zhen-Cheng Wu , Pi-Tsung Chen
发明人： Yung-Cheng Lu , Ying-Tsung Chen , Zhen-Cheng Wu , Pi-Tsung Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/0234 , H01L21/02362 , H01L21/3122 , H01L21/3148 , H01L21/31695 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76846 , H01L21/7685 , H01L2221/1047
摘要： A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene copper conductor and depositing a semipermeable cap layer. In alternative embodiments, the cap layer consists essentially of silicon carbide, silicon nitride, Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof. The semipermeable cap layer is preferably deposited under PECVD conditions such that the cap layer is sufficiently permeable to enable removal of porogen degradation by-products. Preferred embodiments further include an in-situ N2/NH3 treatment before depositing the semipermeable cap layer.
摘要翻译：提供一种制造具有多孔低k电介质层的半导体器件的方法。优选的实施方案包括在镶嵌工艺中形成含致孔剂的低k电介质层的步骤。在优选的实施方案中，通过电子束致孔剂降解的孔产生在CMP平坦化镶嵌铜导体并沉积半透膜盖层的步骤之后发生。在替代实施例中，盖层基本上由碳化硅，氮化硅，Co，W，Al，Ta，Ti，Ni，Ru及其组合组成。半透膜盖层优选在PECVD条件下沉积，使得盖层具有足够的可渗透性以能够除去致孔剂降解副产物。优选实施方案还包括在沉积半透膜盖层之前的原位N 2 / NH 3 N 3处理。

44. 发明授权

US07056826B2 Method of forming copper interconnects 失效
标题翻译：形成铜互连的方法
公开(公告)号：US07056826B2
公开(公告)日：2006-06-06
申请号：US10337684
申请日：2003-01-07
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Ying-Tsung Chen , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Ying-Tsung Chen , Syun-Ming Jang
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/7684 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming copper interconnects for an integrated circuit is provided. An antireflective coating layer is formed over an insulating layer formed over a semiconductor substrate. An interconnect pattern is patterned and etched into said insulating layer. A diffusion barrier layer is then conformally deposited in a deposition chamber along the etched interconnect pattern, wherein the antireflective coating is removed in said chamber before deposition of the barrier layer. Copper interconnects are then formed in the interconnect pattern etched in the insulating layer.
摘要翻译：提供一种形成用于集成电路的铜互连的方法。在半导体衬底上形成的绝缘层上形成抗反射涂层。将互连图案图案化并蚀刻到所述绝缘层中。然后沿着蚀刻的互连图案将扩散阻挡层共形沉积在沉积室中，其中在沉积阻挡层之前在所述室中去除抗反射涂层。然后在绝缘层中蚀刻的互连图案中形成铜互连。

45. 发明申请

US20050236694A1 Silicon oxycarbide and silicon carbonitride based materials for MOS devices 有权
标题翻译：用于MOS器件的碳氧化硅和碳氮化硅基材料
公开(公告)号：US20050236694A1
公开(公告)日：2005-10-27
申请号：US10895514
申请日：2004-07-21
申请人： Zhen-Cheng Wu , H. Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Liang
发明人： Zhen-Cheng Wu , H. Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Liang
IPC分类号： H01L21/31 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/768 , H01L23/31 , H01L23/58 , H01L29/49
CPC分类号： H01L29/4983 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/314 , H01L21/3148 , H01L21/31633 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/3192 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.
摘要翻译：在优选实施例中，在基板上形成栅极电介质和电极。在栅电极和栅极电介质的相对侧壁上形成一对间隔物。间隔物优选由SiCO基材料或SiCN基材料形成。然后形成源极和漏极。在源极/漏极区域和间隔物上形成接触蚀刻停止层（CES）层。 CES层优选由SiCO基材料或SiCN基材料形成。然后在CES层上形成级间介质（ILD）。

46. 发明授权

US06878621B2 Method of fabricating barrierless and embedded copper damascene interconnects 失效
标题翻译：制造无障碍和嵌入铜大马士革互连的方法
公开(公告)号：US06878621B2
公开(公告)日：2005-04-12
申请号：US10346382
申请日：2003-01-17
申请人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76832 , H01L21/76835 , H01L21/76885
摘要： A method for forming at least one barrierless, embedded metal structure comprising the following steps. A structure having a patterned dielectric layer formed thereover with at least one opening exposing at least one respective portion of the structure. Respective metal structures are formed within each respective opening. The first dielectric layer is removed to expose the top and at least a portion of the side walls of the respective at least one metal structure. A dielectric barrier layer is formed over the structure and the exposed top of the respective metal structure. A second, conformal dielectric layer is formed over the dielectric barrier layer to complete the respective barrierless at least one metal structure embedded within the second, conformal dielectric layer. The dielectric barrier layer preventing diffusion of the metal comprising the respective at least one metal structure into the second, conformal dielectric layer.
摘要翻译：一种形成至少一个无障碍嵌入金属结构的方法，包括以下步骤。具有形成在其上的图案化电介质层的结构，其中至少一个开口暴露出结构的至少一个相应部分。在每个相应的开口内形成相应的金属结构。去除第一电介质层以暴露相应的至少一个金属结构的顶部和至少一部分侧壁。介电阻挡层形成在相应的金属结构的结构和暴露的顶部上。在电介质阻挡层上方形成第二个保形介电层，以完成嵌入在第二保形电介质层内的相应无障碍的至少一个金属结构。电介质阻挡层防止包含相应的至少一种金属结构的金属扩散到第二保形电介质层中。

47. 发明申请

US20130192658A1 SOLAR PANEL MODULE 审中-公开
标题翻译：太阳能面板模块
公开(公告)号：US20130192658A1
公开(公告)日：2013-08-01
申请号：US13445922
申请日：2012-04-13
申请人： Huang-Chi Tseng , Chiuan-Ting Li , Wei-Jieh Lee , Chun-Ming Yang , Kuan-Wen Tung , Ming-Yuan Huang , Zhen-Cheng Wu
发明人： Huang-Chi Tseng , Chiuan-Ting Li , Wei-Jieh Lee , Chun-Ming Yang , Kuan-Wen Tung , Ming-Yuan Huang , Zhen-Cheng Wu
IPC分类号： H01L31/052
CPC分类号： H02S20/24 , F24S25/10 , F24S25/70 , H02S20/23 , Y02B10/12 , Y02E10/47
摘要： A solar panel module includes a solar panel, a supporting stand and a deflecting device. The supporting stand is structurally connected to the solar panel for supporting the solar panel. The solar panel is disposed inclinedly, and the solar panel has a tilt angle with respect to a horizontal plane. The deflecting device is disposed underneath the solar panel for deflecting wind blowing from lateral directions toward a wind exiting direction, which faces a bottom surface of the solar panel.
摘要翻译：太阳能电池板模块包括太阳能电池板，支撑架和偏转装置。支撑架结构上连接到用于支撑太阳能电池板的太阳能电池板。太阳能电池板倾斜地设置，太阳能电池板相对于水平面具有倾斜角。偏转装置设置在太阳能面板下方，用于将从侧向吹向风向风朝向太阳能电池板底面的风出风方向偏转。

48. 发明授权

US08084328B2 Semiconductor device including I/O oxide nitrided core oxide on substrate 有权
标题翻译：在衬底上包括I / O氧化物氮化核心氧化物的半导体器件
公开(公告)号：US08084328B2
公开(公告)日：2011-12-27
申请号：US12923889
申请日：2010-10-13
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
IPC分类号： H01I21/8234
CPC分类号： H01L21/823462 , H01L27/088 , Y10S438/981
摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要翻译：半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的芯区域和用于外围电路的外围区域。半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物，以及I / O氧化物上的第二多晶硅图案。

49. 发明申请

US20070249159A1 Method for forming dielectric film to improve adhesion of low-k film 有权
标题翻译：用于形成介电膜以改善低k膜的粘附性的方法
公开(公告)号：US20070249159A1
公开(公告)日：2007-10-25
申请号：US11409658
申请日：2006-04-24
申请人： Fang Tsai , I-I Chen , Zhen-Cheng Wu , Chih-Lung Lin , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
发明人： Fang Tsai , I-I Chen , Zhen-Cheng Wu , Chih-Lung Lin , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/76843
摘要： A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer over an initial sub-layer, and wherein the transition sub-layer has a composition that gradually changes from a lower portion to an upper portion. A low-k dielectric layer is formed on the adhesion layer. Damascene openings are formed in the low-k dielectric layer. A top portion of the transition sub-layer has a composition substantially similar to a composition of the low-k dielectric layer. A bottom portion of the transition sub-layer has a composition substantially similar to a composition of the initial sub-layer.
摘要翻译：提供了具有改进的低k电介质层和下层之间的粘附性的半导体结构及其形成方法。所述半导体衬底包括半导体衬底上的电介质层，所述电介质层上的粘合层，其中所述粘合层包含初始子层上的过渡子层，并且其中所述过渡子层具有逐渐从下部到上部。在粘合层上形成低k电介质层。在低k电介质层中形成镶嵌开口。过渡子层的顶部具有与低k电介质层的组成基本相似的组成。过渡子层的底部具有与初始子层的组成基本相似的组成。

50. 发明申请

US20070054494A1 Method for planarizing semiconductor structures 有权
标题翻译：半导体结构平面化方法
公开(公告)号：US20070054494A1
公开(公告)日：2007-03-08
申请号：US11226979
申请日：2005-09-15
申请人： Ying-Tsung Chen , Yung-Cheng Lu , Zhen-Cheng Wu , Pi-Tsung Chen
发明人： Ying-Tsung Chen , Yung-Cheng Lu , Zhen-Cheng Wu , Pi-Tsung Chen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31053 , H01L22/20
摘要： A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.
摘要翻译：公开了一种用于平面化半导体结构的方法。提供具有第一区域的半导体衬底，其中以第一图案密度形成一个或多个沟槽，以及第二区域，其中以比第一图案密度低的第二图案密度形成一个或多个沟槽。第一介电层形成在半导体上方，用于覆盖第一和第二区域中的沟槽。使用用于减小其厚度的预定类型的浆料在第一介电层上进行第一化学机械抛光。然后冲洗第一介电层。使用预定类型的浆料在第一介电层上进行第二化学机械抛光，用于进一步去除沟槽外的第一介电层，从而降低第一和第二区域的表面之间的台阶高度变化。

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