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41. 发明授权

US06177729B1 Rolling ball connector 失效
标题翻译：滚球连接器
公开(公告)号：US06177729B1
公开(公告)日：2001-01-23
申请号：US09303290
申请日：1999-04-03
申请人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
发明人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
IPC分类号： H01L2348
CPC分类号： H01L24/16 , G01R1/0483 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/83 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/11003 , H01L2224/11334 , H01L2224/13099 , H01L2224/13111 , H01L2224/1319 , H01L2224/17051 , H01L2224/2919 , H01L2224/8319 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H05K1/111 , H05K3/321 , H05K2201/0133 , H05K2201/0212 , H05K2201/0221 , H05K2201/0233 , H05K2201/10234 , H05K2201/10734 , H05K2201/10992 , H05K2203/0307 , Y10T428/12472 , H01L2924/00 , H01L2924/3512 , H01L2924/00014
摘要： An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.
摘要翻译：集成电路组件具有与滚动金属球电连接到衬底的焊盘的芯片焊盘。柔韧的材料将球与芯片和衬底的焊盘可动地接触。由于球相对自由移动，因此在现有技术的连接接头中通常会引起巨大应力的热膨胀差异简单地导致本发明的滚珠滚动，从而完全避免热应力。与C4焊料凸块相比，连接的可靠性大大提高，尽管存在大量的热失配，芯片可以安全地直接安装到诸如PC板的基板上。

42. 发明授权

US6111425A Very low power logic circuit family with enhanced noise immunity 有权
标题翻译：超低功耗逻辑电路系列，具有增强的抗噪声能力
公开(公告)号：US6111425A
公开(公告)日：2000-08-29
申请号：US173436
申请日：1998-10-15
申请人： Claude L. Bertin , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K19/003 , H03K3/356 , H03K19/173 , H03K17/16
CPC分类号： H03K3/356113 , H03K19/1738
摘要： A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.
摘要翻译：一个非常低功率的逻辑电路系列，有利地提供1）保持高性能，2）显着降低的功耗，和3）增强的抗噪声能力。在第一组实施例中，使用双轨互补逻辑信号来提高对外部噪声的电路抗扰性并且减少由逻辑电路本身产生的噪声。本发明的接收机部分包括具有两个门到两个源的交叉耦合的两个输入FET。在一个优选实施例中，接收器和驱动器部分都连接在具有所有N个通道驱动器的中继器中。第二组实施例在不平衡接收机中具有单侧输入，包括到栅极N沟道的交叉耦合源极和栅极P沟道输出晶体管的交叉耦合漏极。

43. 发明授权

US06388305B1 Electrically programmable antifuses and methods for forming the same 有权
标题翻译：电子可编程反熔丝及其形成方法
公开(公告)号：US06388305B1
公开(公告)日：2002-05-14
申请号：US09466495
申请日：1999-12-17
申请人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
发明人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
IPC分类号： H01L2900
CPC分类号： H01L21/763 , H01L23/5252 , H01L27/10861 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a first dielectric material lining the interior surface and a second dielectric material filling the lined trench. The second logic element further comprises a dielectric layer formed over a portion of the first layer and contacting the first dielectric material lining the trench at a merge location; and an electrode extending over a portion of both the dielectric layer and the filled trench. The second logic element is configured so that a predetermined voltage or higher applied between the electrode and the first layer causes a breakdown near the merge location.
摘要翻译：首先，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该第一导电类型的半导体衬底包括在衬底的表面下面的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。第二次，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该半导体衬底包括形成在衬底的表面中的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。沟槽包括内表面，衬在内表面的第一电介质材料和填充衬里沟槽的第二电介质材料。第二逻辑元件还包括形成在第一层的一部分上并且在合并位置处接触衬套在沟槽上的第一介电材料的电介质层; 以及在电介质层和填充沟槽的一部分上延伸的电极。第二逻辑元件被配置为使得施加在电极和第一层之间的预定电压或更高的电压导致合并位置附近的击穿。

44. 发明授权

US06812122B2 Method for forming a voltage programming element 有权
标题翻译：用于形成电压编程元件的方法
公开(公告)号：US06812122B2
公开(公告)日：2004-11-02
申请号：US10095889
申请日：2002-03-12
申请人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
发明人： Claude L. Bertin , Erik L. Hedberg , Russell J. Houghton , Max G. Levy , Rick L. Mohler , William R. Tonti , Wayne M. Trickle
IPC分类号： H01L2144
CPC分类号： H01L21/763 , H01L23/5252 , H01L27/10861 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： Method for forming a first one time, voltage programmable logic element in a semiconductor substrate of first conductivity type, forming a first layer beneath a surface of the substrate, the first layer having a second conductivity type. A trench is formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench.
摘要翻译：用于形成第一导电类型的半导体衬底中的第一次电压可编程逻辑元件的方法，在所述衬底的表面下方形成第一层，所述第一层具有第二导电类型。沟槽通过表面形成并穿过第一层。沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。

45. 发明授权

US06437385B1 Integrated circuit capacitor 失效
标题翻译：集成电路电容
公开(公告)号：US06437385B1
公开(公告)日：2002-08-20
申请号：US09607094
申请日：2000-06-29
申请人： Claude L. Bertin , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10832 , H01L28/55 , H01L28/87 , H01L29/66181 , H01L29/945
摘要： Use of different materials for different conductive films forming plates or electrodes of one or more capacitors formed in a trench in a body of semiconductor materials allow connections to be made selectively to the plates. The films may be undercut by different etchants at respective connection apertures to avoid formation of connections or connections made by doped polysilicon of different conductivities forming connections to some plates of similarly doped polysilicon and blocking diode junctions with oppositely doped polysilicon. The blocking diodes may include a compensation implant to adjust reverse breakdown characteristics and provide transient and electrostatic discharge protection.
摘要翻译：对于形成在半导体材料体中的沟槽中的一个或多个电容器形成板或不同导电膜的不同材料的使用允许选择性地连接板。这些膜可能在相应的连接孔处被不同的蚀刻剂削弱，以避免由不同导电性的掺杂多晶硅形成的连接或连接形成连接到具有相反掺杂多晶硅的类似掺杂多晶硅和阻塞二极管结的某些平板。阻塞二极管可以包括补偿注入以调整反向击穿特性并提供瞬态和静电放电保护。

46. 发明授权

US07394268B2 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07394268B2
公开(公告)日：2008-07-01
申请号：US11531140
申请日：2006-09-12
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/02
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。

47. 发明授权

US06633055B2 Electronic fuse structure and method of manufacturing 有权
标题翻译：电子熔断器结构及制造方法
公开(公告)号：US06633055B2
公开(公告)日：2003-10-14
申请号：US09303509
申请日：1999-04-30
申请人： Claude L. Bertin , Erik L. Hedberg , Max G. Levy , Timothy D. Sullivan , William R. Tonti
发明人： Claude L. Bertin , Erik L. Hedberg , Max G. Levy , Timothy D. Sullivan , William R. Tonti
IPC分类号： H01L2974
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A gap conductor structure for an integrated electronic circuit that may function as an electronic fuse device or as a low capacitance inter level signal line is integrated as part of the semi-conductor chip wiring. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to melt a part of the conducting line. The presence of gaps, and hence, the fuses, are scalable and may be tailored to the capacity of currents they must carry with the characteristics of the fuses defined by a circuit designer. Furthermore, conducting structures completely or partially exposed in the air gap may function as low capacitance minimum delay transmission lines.
摘要翻译：作为半导体芯片布线的一部分，集成电子电路的可用作电子熔断器件或低电容级间信号线的间隙导体结构被集成。间隙导电结构包括一个或多个预定体积的气隙区域，其完全或部分地暴露IC中的层间导体层的长度。或者，气隙区域可以完全位于相应导体下方的电介质区域内并被绝缘体分隔开。当用作熔丝时，间隙区域用于降低远离导体的暴露部分的热导率，使得能够以较低的施加电压在导线中产生更高的热流，从而熔化导电线的一部分。间隙的存在以及保险丝的存在是可扩展的，并且可以根据电路设计者定义的保险丝的特性来适应其必须携带的电流的容量。此外，在气隙中完全或部分暴露的导电结构可用作低电容最小延迟传输线

48. 发明授权

US06358627B2 Rolling ball connector 有权
标题翻译：滚球连接器
公开(公告)号：US06358627B2
公开(公告)日：2002-03-19
申请号：US09768112
申请日：2001-01-23
申请人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
发明人： Joseph A. Benenati , Claude L. Bertin , William T. Chen , Thomas E. Dinan , Wayne F. Ellis , Wayne J. Howell , John U. Knickerbocker , Mark V. Pierson , William R. Tonti , Jerzy M. Zalesinski
IPC分类号： H01L2144
CPC分类号： H01L24/16 , G01R1/0483 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/83 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/11003 , H01L2224/11334 , H01L2224/13099 , H01L2224/13111 , H01L2224/1319 , H01L2224/17051 , H01L2224/2919 , H01L2224/8319 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/3025 , H01L2924/351 , H05K1/111 , H05K3/321 , H05K2201/0133 , H05K2201/0212 , H05K2201/0221 , H05K2201/0233 , H05K2201/10234 , H05K2201/10734 , H05K2201/10992 , H05K2203/0307 , Y10T428/12472 , H01L2924/00 , H01L2924/3512 , H01L2924/00014
摘要： An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.
摘要翻译：集成电路组件具有与滚动金属球电连接到衬底的焊盘的芯片焊盘。柔韧的材料将球与芯片和衬底的焊盘可动地接触。由于球相对自由移动，因此在现有技术的连接接头中通常会引起巨大应力的热膨胀差异简单地导致本发明的滚珠滚动，从而完全避免热应力。与C4焊料凸块相比，连接的可靠性大大提高，尽管存在大量的热失配，芯片可以安全地直接安装到诸如PC板的基板上。

49. 发明授权

US6097241A ASIC low power activity detector to change threshold voltage 有权
标题翻译： ASIC低功率活动检测器来改变阈值电压
公开(公告)号：US6097241A
公开(公告)日：2000-08-01
申请号：US159898
申请日：1998-09-24
申请人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1/32 , H03K3/01
CPC分类号： G06F1/3203 , G06F1/3296 , Y02B60/1285
摘要： An integrated circuit such as an ASIC device having partitioned functional units with independent threshold voltage control. A first partition is always operated in a normal mode, while subsequent partitions are maintained in a standby mode until a transition is detected at the input of the first partition. The subsequent partitions are switched to the normal mode by lowering the body voltage applied to the devices with each partition. A pulse stretcher is used to keep a partition in a normal mode for a predetermined period of time after the transition is detected.
摘要翻译：诸如具有独立阈值电压控制的具有分区功能单元的ASIC器件的集成电路。第一分区总是以正常模式操作，而后续分区保持在待机模式，直到在第一分区的输入处检测到转换。随后的分区通过降低施加到每个分区的设备的体电压而切换到正常模式。在检测到转换之后，使用脉冲展开器将分区保持在正常模式下预定的时间段。

50. 发明授权

US07132841B1 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07132841B1
公开(公告)日：2006-11-07
申请号：US09588617
申请日：2000-06-06
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier. The carrier is formed of a flex material. It can also be formed of printed circuit board material. A window in the flex permits invoking redundancy on each chip after burn-in is complete, significantly improving yield as compared with present schemes that do not permit repair after burn-in.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。载体由柔性材料形成。它也可以由印刷电路板材料形成。柔性窗口允许在烧坏完成后在每个芯片上调用冗余度，与不允许在老化后修复的现有方案相比，显着提高产量。

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