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41. 发明授权

US07087499B2 Integrated antifuse structure for FINFET and CMOS devices 有权
标题翻译：用于FINFET和CMOS器件的集成反熔丝结构
公开(公告)号：US07087499B2
公开(公告)日：2006-08-08
申请号：US10539333
申请日：2002-12-20
申请人： Jed H. Rankin , Wagdi W. Abadeer , Jeffrey S. Brown , William R. Tonti
发明人： Jed H. Rankin , Wagdi W. Abadeer , Jeffrey S. Brown , William R. Tonti
IPC分类号： H01L21/76
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/785
摘要： A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111–114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t–114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).
摘要翻译：描述了与半导体器件（例如FINFET或平面CMOS器件）集成的制造和反熔丝结构（100）的方法。设置在设置在基板（10）上的绝缘体（3）上的半导体材料（11）的区域; 蚀刻工艺暴露了半导体材料中的多个拐角（111-114）。露出的角部被氧化，以形成角落处的细长尖端（111t-114t）; 去除顶部上方的氧化物（31）。然后在半导体材料上形成氧化物层（例如栅极氧化物），并覆盖在角部上; 该层在拐角处具有减小的厚度。在角部处形成与氧化物层（51）接触的导电材料层（60），从而通过氧化物层在半导体材料和导电材料层之间形成多个可能的击穿路径。将诸如老化电压的电压施加到结构将至少一个击穿路径转换成导电路径（103,280）。

42. 发明授权

US06982591B2 Method and circuit for compensating for tunneling current 失效
标题翻译：用于补偿隧道电流的方法和电路
公开(公告)号：US06982591B2
公开(公告)日：2006-01-03
申请号：US10731298
申请日：2003-12-09
申请人： Wagdi W. Abadeer , Jennifer E. Appleyard , John A. Fifield , William R. Tonti
发明人： Wagdi W. Abadeer , Jennifer E. Appleyard , John A. Fifield , William R. Tonti
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/242
摘要： A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.
摘要翻译：一种用于隧道泄漏电流补偿的方法和电路，所述方法包括：通过隧道电流泄漏监测装置强制已知值的电流以提供电压信号; 以及基于所述电压信号来调节所述集成电路芯片的片上电源。

43. 发明授权

US06326732B1 Apparatus and method for non-contact stress evaluation of wafer gate dielectric reliability 有权
标题翻译：晶圆栅介质可靠性非接触应力评估装置及方法
公开(公告)号：US06326732B1
公开(公告)日：2001-12-04
申请号：US09250880
申请日：1999-02-16
申请人： Wagdi W. Abadeer , Eduard A. Cartier , James H. Stathis
发明人： Wagdi W. Abadeer , Eduard A. Cartier , James H. Stathis
IPC分类号： H01J724
CPC分类号： G01R31/2623 , G01R31/275
摘要： An apparatus and method for evaluating the performance of a test dielectric material for use as a gate dielectric. The method comprises exposing a coated layer of the dielectric to a concentration of atomic hydrogen. The method may comprise (a) measuring an initial value of interface-state density in the test dielectric, (b) exposing the coated test dielectric to a concentration of atomic hydrogen in a remote plasma, and then (c) measuring a post-exposure value of interface-state density in the test dielectric. Steps (b) and (c) may be repeated with incrementally higher concentrations of atomic hydrogen to determine a rate of change in interface-state density value as a function of atomic hydrogen concentration, which may then be related to the projected charge-to-breakdown or time-to-breakdown of the test dielectric layer when the dielectric is used as the gate dielectric. The method may be conducted on a remote-plasma hydrogen exposure apparatus comprising, in series, a source of a mixture of molecular and atomic hydrogen gas; a particle remover adapted to remove energetic, charged particles; a light sink; a hydrogen recombination device; and a wafer exposure chamber.
摘要翻译：用于评估用作栅极电介质的测试电介质材料的性能的装置和方法。该方法包括将电介质的涂层暴露于原子氢浓度。该方法可以包括（a）测量测试电介质中的界面态密度的初始值，（b）将涂覆的测试电介质暴露于远程等离子体中的原子氢浓度，然后（c）测量曝光后测试电介质中界面态密度的值。步骤（b）和（c）可以用逐渐增加的原子氢浓度重复，以确定作为原子氢浓度的函数的界面态密度值的变化率，其然后可能与预计的电荷 - 当电介质用作栅极电介质时，测试电介质层的击穿或击穿时间。该方法可以在远程等离子体氢曝光装置上进行，该装置包括串联的分子和原子氢气混合物的源; 适于去除高能充电颗粒的颗粒去除剂; 一个光汇氢复合装置; 和晶片曝光室。

44. 发明授权

US5334880A Low voltage programmable storage element 失效
标题翻译：低电压可编程存储元件
公开(公告)号：US5334880A
公开(公告)日：1994-08-02
申请号：US693463
申请日：1991-04-30
申请人： Wagdi W. Abadeer , Badih El-Kareh , Wayne F. Ellis , Duane E. Galbi , Nathan R. Hiltebeitel , William R. Tonti , Josef S. Watts
发明人： Wagdi W. Abadeer , Badih El-Kareh , Wayne F. Ellis , Duane E. Galbi , Nathan R. Hiltebeitel , William R. Tonti , Josef S. Watts
IPC分类号： G11C11/413 , G11C11/401 , G11C17/00 , G11C17/06 , G11C17/14 , G11C17/16 , G11C29/00 , G11C29/04 , H01L27/10 , G11C11/34 , G11C7/00 , G11C11/40 , H01L29/04
CPC分类号： G11C29/785 , G11C17/14 , G11C17/16
摘要： A programmable storage element for redundancy-programming includes a programmable antifuse circuit, which includes a plurality of first resistors and a switching circuit for coupling the first resistors in series in response to a plurality of first control signals and for coupling the first resistors in parallel in response to a plurality of second control signals to permit programming of the first resistors, and a sensing circuit for determining whether or not the first resistors have been programmed. The state of the first resistors is determined by comparing a first voltage drop across the first resistors with a second voltage drop across a second resistor. Each of the first resistors is an unsilicided polysilicon conductor which has an irreversible resistance decrease when a predetermined threshold current is applied for a minimum period of time.
摘要翻译：用于冗余编程的可编程存储元件包括可编程反熔丝电路，其包括多个第一电阻器和用于响应于多个第一控制信号串联耦合第一电阻器并用于将第一电阻器并联耦合的开关电路响应于多个第二控制信号以允许对第一电阻器进行编程;以及感测电路，用于确定第一电阻器是否已被编程。第一电阻器的状态通过将第一电阻器两端的第一电压降与第二电阻器上的第二电压降进行比较来确定。每个第一电阻器是非极性多晶硅导体，当预定阈值电流施加最小时间时，其具有不可逆电阻降低。

45. 发明授权

US08349697B2 Field effect transistor with air gap dielectric 有权
标题翻译：具有气隙电介质的场效应晶体管
公开(公告)号：US08349697B2
公开(公告)日：2013-01-08
申请号：US13537334
申请日：2012-06-29
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti , Yun Shi
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti , Yun Shi
IPC分类号： H01L21/76
CPC分类号： H01L29/66795 , H01L29/785
摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
摘要翻译：一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。门通过气隙与身体的至少一部分分离。气隙也在第一平面。

46. 发明申请

US20120264275A1 FIELD EFFECT TRANSISTOR WITH AIR GAP DIELECTRIC 有权
标题翻译：具有气隙介质的场效应晶体管
公开(公告)号：US20120264275A1
公开(公告)日：2012-10-18
申请号：US13537334
申请日：2012-06-29
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , William R. Tonti , Yun Shi
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , William R. Tonti , Yun Shi
IPC分类号： H01L21/762
CPC分类号： H01L29/66795 , H01L29/785
摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
摘要翻译：一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。门通过气隙与身体的至少一部分分离。气隙也在第一平面。

47. 发明授权

US08110483B2 Forming an extremely thin semiconductor-on-insulator (ETSOI) layer 有权
标题翻译：形成极薄的绝缘体上半导体（ETSOI）层
公开(公告)号：US08110483B2
公开(公告)日：2012-02-07
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal, legal representative , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

48. 发明授权

US08021950B1 Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation 有权
标题翻译：半导体晶片处理方法允许器件区域在线后面（BEOL）金属布线层形成之后被选择性地退火
公开(公告)号：US08021950B1
公开(公告)日：2011-09-20
申请号：US12911940
申请日：2010-10-26
申请人： Wagdi W. Abadeer , Lilian Kamal, legal representative , John J. Ellis-Monaghan , Jeffrey P. Gambino , Tom C. Lee
发明人： Wagdi W. Abadeer , John J. Ellis-Monaghan , Jeffrey P. Gambino , Tom C. Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/28044 , H01L21/268 , H01L29/1054 , H01L29/4925 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring formation without degrading wiring layer reliability. In the embodiments, a semiconductor device is formed adjacent to the top surface of a wafer such that it incorporates a selectively placed infrared absorbing layer (IAL). Then, following BEOL metal wiring formation, the bottom surface of the wafer is exposed to an infrared light having a wavelength that is transparent to the wafer. The infrared light is absorbed by and, thereby heats up the IAL to a first predetermined temperature (e.g., a dopant activation temperature, a temperature required for a state change, etc.). The resulting heat is transferred from the IAL to an adjacent region of the semiconductor device without raising the temperature of the metal wiring above a second predetermined temperature (e.g., a temperature that could degrade the metal wiring) that is lower than the first predetermined temperature.
摘要翻译：公开了允许器件区域在线路后端（BEOL）金属布线形成之后选择性退火的半导体晶片处理方法的实施例，而不会降低布线层的可靠性。在实施例中，半导体器件形成为与晶片的顶表面相邻，使得其结合有选择放置的红外线吸收层（IAL）。然后，在BEOL金属布线形成之后，晶片的底面暴露于对晶片透明的波长的红外光。红外光被IAL吸收，从而将IAL加热到第一预定温度（例如，掺杂剂活化温度，状态改变所需的温度等）。所产生的热量从IAL转移到半导体器件的相邻区域，而不会将金属布线的温度升高到低于第一预定温度的第二预定温度（例如，可能降低金属布线的温度）。

49. 发明申请

US20110073985A1 Method of Generating Uniformly Aligned Well and Isolation Regions in a Substrate and Resulting Structure 有权
标题翻译：在基板和结构中产生均匀排列的井和隔离区域的方法
公开(公告)号：US20110073985A1
公开(公告)日：2011-03-31
申请号：US12570415
申请日：2009-09-30
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William Tonti
IPC分类号： H01L29/06 , H01L23/00 , H01L21/762
CPC分类号： H01L21/76232
摘要： A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.
摘要翻译：本文描述了用于减小缩放半导体技术中的可变寄生双极性泄漏的解决方案。在浅沟槽隔离（STI）区域下的植入物的边缘，通过与仅使用标准光刻掩模相比更加精确地产生屏蔽区域而不是植入屏蔽区域来消除放置变化。退火处理使注入区域扩展，使其边界在与沟槽边缘预定距离内对齐。距离对于每个沟槽和每个相邻的隔离区域是成比例的。

50. 发明授权

US07791010B2 CMOS image sensor having a third FET device with the gate terminal coupled to the diffusion region of a first FET device, the second terminal coupled to a column signal line, and the first terminal coupled to a row select signal 有权
标题翻译： CMOS图像传感器具有第三FET器件，栅极端子耦合到第一FET器件的扩散区域，第二端子耦合到列信号线，第一端子耦合到行选择信号
公开(公告)号：US07791010B2
公开(公告)日：2010-09-07
申请号：US12117159
申请日：2008-05-08
申请人： Wagdi W. Abadeer
发明人： Wagdi W. Abadeer
IPC分类号： H01L27/00
CPC分类号： H04N5/361 , H01L27/14609 , H01L27/14645 , H04N5/37213 , H04N5/3741
摘要： A design structure for a CMOS image sensor and active pixel cell design that provides an output signal representing an incident illumination light level that is adapted for time domain analysis. Thus, the noise sources associated with charge integration and the contribution of dark current to it, is avoided. The active pixel cell design implements only three FETs: a transfer device, a reset device and an output transistor device having one diffusion connected to a Row Select signal. In this mode of operation, use is made of the voltage decay at the photo diode to generate a pixel output at one diffusion of the output transistor device, which is a pulse with fixed amplitude independent of the incident illumination level. For use of an NFET output transistor device, the pulse width is an inverse function of the incident illumination level. For a PFET output transistor device, the output pulse has a time delay, from a reference signal, by an amount that is an inverse function of the incident illumination level.
摘要翻译：用于CMOS图像传感器和有源像素单元设计的设计结构，其提供表示适于时域分析的入射照明光水平的输出信号。因此，避免了与电荷积分相关的噪声源和暗电流对其的贡献。有源像素单元设计仅实现三个FET：传输装置，复位装置和具有连接到行选择信号的一个扩散的输出晶体管装置。在这种操作模式中，使用光电二极管处的电压衰减，以在输出晶体管器件的一个扩散处产生像素输出，输出晶体管器件是具有独立于入射照明电平的固定振幅的脉冲。对于使用NFET输出晶体管器件，脉冲宽度是入射照明电平的反函数。对于PFET输出晶体管器件，输出脉冲具有来自参考信号的时间延迟与入射照明电平的反函数的量。

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