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1. 发明授权

US08021950B1 Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation 有权
标题翻译：半导体晶片处理方法允许器件区域在线后面（BEOL）金属布线层形成之后被选择性地退火
公开(公告)号：US08021950B1
公开(公告)日：2011-09-20
申请号：US12911940
申请日：2010-10-26
申请人： Wagdi W. Abadeer , Lilian Kamal, legal representative , John J. Ellis-Monaghan , Jeffrey P. Gambino , Tom C. Lee
发明人： Wagdi W. Abadeer , John J. Ellis-Monaghan , Jeffrey P. Gambino , Tom C. Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/28044 , H01L21/268 , H01L29/1054 , H01L29/4925 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring formation without degrading wiring layer reliability. In the embodiments, a semiconductor device is formed adjacent to the top surface of a wafer such that it incorporates a selectively placed infrared absorbing layer (IAL). Then, following BEOL metal wiring formation, the bottom surface of the wafer is exposed to an infrared light having a wavelength that is transparent to the wafer. The infrared light is absorbed by and, thereby heats up the IAL to a first predetermined temperature (e.g., a dopant activation temperature, a temperature required for a state change, etc.). The resulting heat is transferred from the IAL to an adjacent region of the semiconductor device without raising the temperature of the metal wiring above a second predetermined temperature (e.g., a temperature that could degrade the metal wiring) that is lower than the first predetermined temperature.
摘要翻译：公开了允许器件区域在线路后端（BEOL）金属布线形成之后选择性退火的半导体晶片处理方法的实施例，而不会降低布线层的可靠性。在实施例中，半导体器件形成为与晶片的顶表面相邻，使得其结合有选择放置的红外线吸收层（IAL）。然后，在BEOL金属布线形成之后，晶片的底面暴露于对晶片透明的波长的红外光。红外光被IAL吸收，从而将IAL加热到第一预定温度（例如，掺杂剂活化温度，状态改变所需的温度等）。所产生的热量从IAL转移到半导体器件的相邻区域，而不会将金属布线的温度升高到低于第一预定温度的第二预定温度（例如，可能降低金属布线的温度）。

2. 发明授权

US08791712B2 3-dimensional integrated circuit testing using MEMS switches with tungsten cone contacts 有权
标题翻译：使用具有钨锥触点的MEMS开关的三维集成电路测试
公开(公告)号：US08791712B2
公开(公告)日：2014-07-29
申请号：US13364345
申请日：2012-02-02
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G01R1/067
CPC分类号： G01R1/06727 , B81B2203/0118 , B81C1/00111 , G01R1/06738 , G01R1/06744 , G01R1/07342 , G01R3/00 , H01L21/76804 , H01L21/76885 , H01L22/14 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).
摘要翻译：一种用于测试多层三维集成电路（IC）的测试系统，其中临时连接两个独立的IC电路层以实现功能性，包括具有三维IC的第一部分的被测芯片，以及测试探针芯片，其具有第三部分的IC和微机电系统（MEMS）开关，其选择性地完成第一IC层中的第三部分的第三部分之间的功能电路和第二部分内的电路的三维IC在第二IC层中。 MEMS开关包括钨（W）锥形触点，其使得被测芯片的电路和测试探针芯片之间的选择性电接触，并且使用梯度硼磷硅酸盐玻璃（BPSG）的模板形成。

3. 发明申请

US20130084476A1 FUSE FOR THREE DIMENSIONAL SOLID-STATE BATTERY 有权
标题翻译：三维固态电池的保险丝
公开(公告)号：US20130084476A1
公开(公告)日：2013-04-04
申请号：US13252366
申请日：2011-10-04
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01M10/42 , H01M10/04
CPC分类号： H01M10/04 , H01M2/204 , H01M2/24 , H01M2/34 , H01M4/767 , H01M10/02 , H01M10/052 , H01M10/0562 , H01M10/42 , Y02E60/12 , Y10T29/49108
摘要： A solid-state battery structure having a plurality of battery cells formed in a substrate, method of manufacturing the same and design structure thereof are provided. The battery structure includes a patterned cathode electrode layer formed upon the substrate and structured to form a plurality of sub-arrays of the battery cells. The battery structure further includes a plurality of fuse wires structured to interconnect at least two adjacent sub-arrays. At least one of the plurality of fuse wires is structured to be blown to disconnect an interconnection having a defective sub-array. Advantageously, the plurality of fuse wires is an integral part of the battery structure.
摘要翻译：提供了具有形成在基板中的多个电池单元的固态电池结构，其制造方法和设计结构。电池结构包括形成在基板上并构造成形成电池单元的多个子阵列的图案化阴极电极层。电池结构还包括构造成互连至少两个相邻子阵列的多个熔丝。多个熔丝中的至少一个被构造成被吹塑以断开具有缺陷子阵列的互连。有利的是，多个熔丝是电池结构的组成部分。

4. 发明授权

US08232215B2 Spacer linewidth control 有权
标题翻译：间隔线宽控制
公开(公告)号：US08232215B2
公开(公告)日：2012-07-31
申请号：US12622557
申请日：2009-11-20
申请人： James A. Culp , Jeffrey P. Gambino , John J. Ellis-Monaghan , Kirk D. Peterson , Jed H. Rankin
发明人： James A. Culp , Jeffrey P. Gambino , John J. Ellis-Monaghan , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01L21/302
CPC分类号： H01L21/31144
摘要： A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.
摘要翻译：用于形成邻接多个均匀间隔的地形特征的多个可变线宽间隔物的方法在位于多个均匀间隔的地形特征之上的间隔物材料层上使用共形抗蚀剂层。保形抗蚀剂层被差异地曝光和显影以提供在形成可变线宽间隔物时用作牺牲掩模的差分厚度抗蚀剂层。用于形成均匀线宽间隔物的方法，其邻接狭窄间隔的地形特征和在相同基底上的宽间隔的地形特征，使用可变厚度间隔物材料层的掩蔽各向同性蚀刻，以提供更均匀的部分蚀刻的间隔物材料层，随后是未掩模的各向异性蚀刻的部分蚀刻的间隔材料层。用于形成均匀线宽间隔物的相关方法使用包括至少一个掩模处理步骤的两步各向异性蚀刻方法。

5. 发明申请

US20120149200A1 NITRIDE ETCH FOR IMPROVED SPACER UNIFORMITY 失效
标题翻译：用于改进间隔均匀的氮化层
公开(公告)号：US20120149200A1
公开(公告)日：2012-06-14
申请号：US12966432
申请日：2010-12-13
申请人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
发明人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L21/28035 , H01L21/76237 , H01L21/823425 , H01L21/823468 , H01L21/823481 , H01L29/78
摘要： A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.
摘要翻译：一种形成电介质间隔物的方法，包括提供包括具有第一多个栅极结构的第一区域和具有第二多个栅极结构的第二区域和至少一种含氧化物的材料或含碳材料的衬底。在第一区域上形成厚度小于存在于第二区域中的含氮化物层的厚度的含氮化物层。在第一多个第二多个栅极结构上从氮化物含有层形成电介质间隔物。所述至少一种含氧化物的材料或含碳材料加速了第二区域中的蚀刻，使得第一区域中的电介质间隔物的厚度基本上等于衬底的第二区域中的电介质间隔物的厚度。

6. 发明授权

US08138534B2 Anti-reflection structures for CMOS image sensors 有权
标题翻译： CMOS图像传感器的防反射结构
公开(公告)号：US08138534B2
公开(公告)日：2012-03-20
申请号：US12770349
申请日：2010-04-29
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/10 , H01L31/112
CPC分类号： H01L31/103 , H01L24/05 , H01L24/73 , H01L27/14603 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/0236 , H01L2224/04042 , H01L2224/05 , H01L2224/32225 , H01L2224/48227 , H01L2224/48464 , H01L2224/4847 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , Y02E10/50 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.
摘要翻译：提供了具有不同折射率的两层之间的突起阵列的光学结构。突起阵列具有小于由CMOS图像传感器的光电二极管可检测的光的波长范围的垂直和侧向尺寸。突起的阵列提供了很少的反射光的高透射率。突起阵列可以设置在光电二极管上，后端行互连结构中，用于光电二极管的透镜，光电二极管的背面或芯片封装的窗口上。

7. 发明授权

US07491992B2 Image sensor cells 失效
标题翻译：图像传感器单元
公开(公告)号：US07491992B2
公开(公告)日：2009-02-17
申请号：US11619024
申请日：2007-01-02
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Richard J. Rassel , Jeffrey P. Gambino
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Richard J. Rassel , Jeffrey P. Gambino
IPC分类号： H01L31/62 , H01L31/113
CPC分类号： H01L27/14609 , H01L27/1463 , H01L27/14641 , H01L27/14643 , H01L31/035281
摘要： A structure (and method for forming the same) for an image sensor cell. The method includes providing a semiconductor substrate. Then, a charge collection well is formed in the semiconductor substrate, the charge collection well comprising dopants of a first doping polarity. Next, a surface pinning layer is formed in the charge collection well, the surface pinning layer comprising dopants of a second doping polarity opposite to the first doping polarity. Then, an electrically conductive push electrode is formed in direct physical contact with the surface pinning layer but not in direct physical contact with the charge collection well. Then, a transfer transistor is formed on the semiconductor substrate. The transfer transistor includes first and second source/drain regions and a channel region. The first and second source/drain regions comprise dopants of the first doping polarity. The first source/drain region is in direct physical contact with the charge collection well.
摘要翻译：用于图像传感器单元的结构（及其形成方法）。该方法包括提供半导体衬底。然后，在半导体衬底中形成电荷收集阱，电荷收集阱包含第一掺杂极性的掺杂剂。接下来，在电荷收集阱中形成表面钉扎层，表面钉扎层包括与第一掺杂极性相反的第二掺杂极性的掺杂剂。然后，导电的推动电极形成为与表面钉扎层直接物理接触，但不与电荷收集阱直接物理接触。然后，在半导体衬底上形成传输晶体管。传输晶体管包括第一和第二源极/漏极区域和沟道区域。第一和第二源/漏区包括第一掺杂极性的掺杂剂。第一源极/漏极区域与电荷收集阱直接物理接触。

8. 发明申请

US20090001427A1 CHARGE CARRIER BARRIER FOR IMAGE SENSOR 审中-公开
标题翻译：用于图像传感器的充电载物障碍物
公开(公告)号：US20090001427A1
公开(公告)日：2009-01-01
申请号：US11770843
申请日：2007-06-29
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe
IPC分类号： H01L27/148 , H01L31/113 , H01L31/18
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14643
摘要： A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell.
摘要翻译：像素传感器结构，制造方法和操作方法。公开了一种缓冲像素单元，其包括用于防止杂散电荷载流子到达暗电流校正像素单元的阻挡区域。缓冲像素单元位于暗电流校正像素单元附近，并且缓冲像素单元类似于有源像素单元。因此，围绕暗电流校正像素单元的环境与有源像素单元周围的环境相似。

9. 发明授权

US08551859B2 Biosensors integrated with a microfluidic structure 有权
标题翻译：与微流体结构集成的生物传感器
公开(公告)号：US08551859B2
公开(公告)日：2013-10-08
申请号：US13293795
申请日：2011-11-10
申请人： Kristin M. Ackerson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Yen L. Lim
发明人： Kristin M. Ackerson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Yen L. Lim
IPC分类号： H01L21/76 , H01L21/70
CPC分类号： G01N27/4145 , H01L29/772
摘要： A biosensor with a microfluidic structure surrounded by an electrode and methods of forming the electrode around the microfluidic structure of the biosensor are provided. A method includes forming a gate or electrode in a first layer. The method further includes forming a trench in a second layer. The method further includes forming a first metal layer in the trench such that the first metal layer is in electrical contact with the gate or the electrode. The method further includes forming a sacrificial material in the trench. The method further includes forming a second metal layer over the sacrificial material and in contact with the first metal layer. The method further includes removing the sacrificial material such that a microfluidic channel is formed surrounded by the first and the second metal layers.
摘要翻译：提供了由电极包围的微流体结构的生物传感器和围绕生物传感器的微流体结构形成电极的方法。一种方法包括在第一层中形成栅极或电极。该方法还包括在第二层中形成沟槽。该方法还包括在沟槽中形成第一金属层，使得第一金属层与栅极或电极电接触。该方法还包括在沟槽中形成牺牲材料。该方法还包括在牺牲材料上形成第二金属层并与第一金属层接触。该方法还包括去除牺牲材料，使得由第一和第二金属层围绕的微流体通道形成。

10. 发明申请

US20130200910A1 3-DIMENSIONAL INTEGRATED CIRCUIT TESTING USING MEMS SWITCHES WITH TUNGSTEN CONE CONTACTS 有权
标题翻译：采用微机电开关的三维集成电路测试
公开(公告)号：US20130200910A1
公开(公告)日：2013-08-08
申请号：US13364345
申请日：2012-02-02
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G01R1/067 , H01L21/768
CPC分类号： G01R1/06727 , B81B2203/0118 , B81C1/00111 , G01R1/06738 , G01R1/06744 , G01R1/07342 , G01R3/00 , H01L21/76804 , H01L21/76885 , H01L22/14 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).
摘要翻译：一种用于测试多层三维集成电路（IC）的测试系统，其中临时连接两个独立的IC电路层以实现功能性，包括具有三维IC的第一部分的被测芯片，以及测试探针芯片，其具有第三部分的IC和微机电系统（MEMS）开关，其选择性地完成第一IC层中的第三部分的第三部分之间的功能电路和第二部分内的电路的三维IC在第二IC层中。 MEMS开关包括钨（W）锥形触点，其使得被测芯片的电路和测试探针芯片之间的选择性电接触，并且使用梯度硼磷硅酸盐玻璃（BPSG）的模板形成。

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