专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US06214683B1 Process for fabricating a semiconductor device component using lateral metal oxidation 有权
标题翻译：使用侧面金属氧化制造半导体器件部件的工艺
公开(公告)号：US06214683B1
公开(公告)日：2001-04-10
申请号：US09290555
申请日：1999-04-12
申请人： Qi Xiang , Scott Allan Bell , Chih-Yuh Yang
发明人： Qi Xiang , Scott Allan Bell , Chih-Yuh Yang
IPC分类号： H01L21336
CPC分类号： H01L21/28123 , H01L21/32139 , H01L29/665
摘要： A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques followed by a lateral oxidation process to reduce the lateral dimension of the hard-mask. The lateral oxidation is carried out by selectively oxidizing an oxidizable layer situated between an etch-stop layer and an oxidation resistant layer. Upon completion of the lateral oxidation process, etch-stop layer and the oxidation resistant are removed and a residual layer of oxidizable material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.
摘要翻译：制造半导体器件的方法包括使用光刻技术形成硬掩膜，然后进行横向氧化处理以减小硬掩模的横向尺寸。侧向氧化通过选择性地氧化位于蚀刻停止层和抗氧化层之间的可氧化层来进行。在完成横向氧化工艺后，去除蚀刻停止层和耐氧化层，然后使用剩余的可氧化材料层作为用于形成器件部件的掩模。残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。

42. 发明授权

US6121155A Integrated circuit fabrication critical dimension control using self-limiting resist etch 有权
标题翻译：使用自限制抗蚀剂蚀刻的集成电路制造临界尺寸控制
公开(公告)号：US6121155A
公开(公告)日：2000-09-19
申请号：US205590
申请日：1998-12-04
申请人： Chih-Yuh Yang , Scott Bell , Qi Xiang
发明人： Chih-Yuh Yang , Scott Bell , Qi Xiang
IPC分类号： H01L21/308 , H01L21/311 , H01L21/8238 , H01L21/302
CPC分类号： H01L21/82385 , H01L21/3088 , H01L21/31116
摘要： The present invention provides a process for self-limiting trim etch of patterned photoresist that will allow integrated circuit fabrication to achieve smaller integrated circuit component features and greatly reduce final critical dimension drift or variation. Trim time is set in a plateau region of the critical dimension loss process curve.
摘要翻译：本发明提供了一种用于图案化光致抗蚀剂的自限制微调蚀刻的方法，其将允许集成电路制造实现更小的集成电路组件特征并大大减少最终临界尺寸漂移或变化。修剪时间设置在临界尺寸损失过程曲线的平台区域。

43. 发明授权

US6103611A Methods and arrangements for improved spacer formation within a semiconductor device 失效
标题翻译：用于改善半导体器件内的间隔物形成的方法和布置
公开(公告)号：US6103611A
公开(公告)日：2000-08-15
申请号：US993830
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L21/311 , H01L21/00 , H01L21/3065
CPC分类号： H01L21/31116
摘要： Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
摘要翻译：提供了在半导体器件内形成间隔物期间增加工艺控制的方法和装置。这些方法和布置包括使用非功能或虚拟线，区域和/或图案来创建导致随后形成的间隔物在形状和尺寸上更可预测和均匀的拓扑。

44. 发明授权

US07183152B1 Epitaxially grown fin for FinFET 有权
标题翻译： FinFET的外延生长鳍
公开(公告)号：US07183152B1
公开(公告)日：2007-02-27
申请号：US10975475
申请日：2004-10-29
申请人： Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
发明人： Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/00 , H01L21/84 , H01L21/3205
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66795 , H01L29/78687
摘要： A method of forming a fin for a fin field effect transistor (FinFET) includes defining a trench in a layer of first material, where a width of an opening of the trench is substantially smaller than a thickness of the layer. The method includes growing a second material in the trench to form the fin and removing the layer of first material.
摘要翻译：形成鳍状场效应晶体管（FinFET）的鳍片的方法包括在第一材料层中限定沟槽，其中沟槽的开口的宽度基本上小于该层的厚度。该方法包括在沟槽中生长第二材料以形成翅片并去除第一材料层。

45. 发明授权

US06790782B1 Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal 有权
标题翻译：包括高K栅极电介质的晶体管栅极的制造工艺，其具有原位抗蚀剂修整，栅极蚀刻和高K电介质去除
公开(公告)号：US06790782B1
公开(公告)日：2004-09-14
申请号：US10157450
申请日：2002-05-29
申请人： Chih-Yuh Yang , Cyrus E. Tabery , Ming-Ren Lin
发明人： Chih-Yuh Yang , Cyrus E. Tabery , Ming-Ren Lin
IPC分类号： H01L21302
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/28273 , H01L29/517
摘要： The invention provides a method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack etch, and removal of exposed regions of the high-K dielectric to be performed efficiently in a single etch chamber. As such, process complexity and processing costs are reduced while throughput and overall process efficiency is improved. The method includes fabricating a high-K gate dielectric etch stop dielectric layer on the surface of a silicon substrate to protect the silicon substrate from erosion during an etch step and to prove a gate dielectric. A polysilicon layer is fabricated above the high-K dielectric layer. An anti-reflective coating layer above the polysilicon layer, and a mask is fabricated above the anti-reflective coating layer to define a gate region and an erosion region. The sequence of etching steps discussed above are performed in-situ in an enclosed high density plasma etching chamber environment.
摘要翻译：本发明提供了在高K栅极电介质的表面上形成小几何形状的栅极的方法。该方法提供了处理步骤，其包括在单个蚀刻室中有效执行的栅极图案修整，栅极堆叠蚀刻和去除高K电介质的暴露区域。因此，降低了处理复杂性和处理成本，同时提高了吞吐量和整体处理效率。该方法包括在硅衬底的表面上制造高K栅电介质蚀刻阻挡介电层，以在蚀刻步骤期间保护硅衬底免受腐蚀并证明栅极电介质。在高K电介质层上方制造多晶硅层。在多晶硅层上方的抗反射涂层和在抗反射涂层上方制造掩模以限定栅极区域和侵蚀区域。上述蚀刻步骤的顺序在封闭的高密度等离子体蚀刻室环境中原位进行。

46. 发明授权

US06773998B1 Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning 有权
标题翻译：改进的薄膜堆叠和图案化策略，用于应力补偿和防止无定形碳栅图案中的图案变形
公开(公告)号：US06773998B1
公开(公告)日：2004-08-10
申请号：US10445129
申请日：2003-05-20
申请人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
发明人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21336
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/31116 , H01L21/3146 , H01L21/32137 , H01L21/32139
摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.
摘要翻译：集成电路的方法包括使用无定形碳ARC掩模。一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

47. 发明授权

US06645797B1 Method for forming fins in a FinFET device using sacrificial carbon layer 有权
标题翻译：在使用牺牲碳层的FinFET器件中形成翅片的方法
公开(公告)号：US06645797B1
公开(公告)日：2003-11-11
申请号：US10310926
申请日：2002-12-06
申请人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
发明人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L2184
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.
摘要翻译：一种在半导体器件中形成翅片的方法，包括：衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电层，包括在导电层上形成碳层，并在碳层上形成掩模。该方法还包括蚀刻掩模和碳层以形成至少一种结构，其中结构具有第一宽度，将至少一个结构中的碳层的宽度减小到第二宽度，沉积氧化物层以围绕至少一个结构，去除所述氧化物层和所述掩模的一部分，除去所述碳层以在所述至少一个结构中的每一个结构的氧化物层的剩余部分中形成开口，用导电材料填充所述至少一个开口并且去除氧化物层的剩余部分和导电层的一部分以形成翅片。

48. 发明授权

US06579809B1 In-situ gate etch process for fabrication of a narrow gate transistor structure with a high-k gate dielectric 有权
标题翻译：用于制造具有高k栅极电介质的窄栅极晶体管结构的原位栅极蚀刻工艺
公开(公告)号：US06579809B1
公开(公告)日：2003-06-17
申请号：US10147623
申请日：2002-05-16
申请人： Chih-Yuh Yang , Cyrus E. Tabery
发明人： Chih-Yuh Yang , Cyrus E. Tabery
IPC分类号： H01L21461
CPC分类号： H01L29/517 , H01L21/0338 , H01L21/28123 , H01L21/28194 , H01L21/31138 , H01L21/32139 , H01L29/511
摘要： The invention provides a method of small geometry gate formation on the surface of a high-k gate dielectric wherein process complexity and processing costs are reduced while throughput and overall process efficiency is improved. The method may utilize photolithography illumination of 157 nm, 193 nm, 248 nm, or other suitable wavelengths to mask a gate region. An aggressive mask trim may be used to reduce the mask size such that it masks a narrow gate region. A hard mask is then fabricated over the narrow gate region and the gate and high-k dielectric are etched to expose the silicon substrate. The entire etch sequence can be performed in-situ within a single gate etch chamber.
摘要翻译：本发明提供了在高k栅极电介质的表面上形成小几何形状的栅极的方法，其中降低了处理复杂性和处理成本，同时提高了处理效率和整体处理效率。该方法可以利用157nm，193nm，248nm或其它合适波长的光刻照明来掩蔽栅极区域。可以使用积极的掩模修整来减小掩模尺寸，使得其掩盖窄的栅极区域。然后在窄栅极区域上制造硬掩模，并蚀刻栅极和高k电介质以暴露硅衬底。整个蚀刻序列可以在单个栅极蚀刻室内原位进行。

49. 发明授权

US06451647B1 Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual 失效
标题翻译：栅极和栅极电介质的等离子体蚀刻和低功率等离子体栅极蚀刻去除高K残留的集成等离子体蚀刻
公开(公告)号：US06451647B1
公开(公告)日：2002-09-17
申请号：US10100819
申请日：2002-03-18
申请人： Chih-Yuh Yang , Minh Van Ngo
发明人： Chih-Yuh Yang , Minh Van Ngo
IPC分类号： H01L218242
CPC分类号： H01L21/28194 , H01L21/2807 , H01L21/28123 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L21/31116 , H01L21/32137 , H01L21/32139 , H01L29/517
摘要： The present invention relates to a process of fabricating a semiconductor device, including steps of providing a first semiconductor wafer; depositing on the first semiconductor wafer a layer comprising a high-K dielectric material layer; depositing on the layer comprising a high-K dielectric material a polysilicon or polysilicon-germanium layer; and forming a gate stack by plasma etching both a portion of the polysilicon or polysilicon-germanium layer and a portion of the layer comprising a high-K dielectric material in a single chamber. In one embodiment, the step of plasma etching is carried out without moving the first wafer from the chamber. In another embodiment an unwanted residual high-K dielectric material is removed by applying a low power plasma treatment.
摘要翻译：本发明涉及制造半导体器件的方法，包括提供第一半导体晶片的步骤; 在第一半导体晶片上沉积包含高K电介质材料层的层; 在包括高K电介质材料的层上沉积多晶硅或多晶硅 - 锗层; 以及通过在单个室中等离子体蚀刻多晶硅或多晶硅 - 锗层的一部分和包含高K电介质材料的层的一部分来形成栅叠层。在一个实施例中，在不从腔室移动第一晶片的情况下执行等离子体蚀刻的步骤。在另一个实施例中，通过施加低功率等离子体处理来去除不想要的残余高K电介质材料。

50. 发明授权

US6133129A Method for fabricating a metal structure with reduced length that is beyond photolithography limitations 失效
标题翻译：用于制造超过光刻限制的具有减小的长度的金属结构的方法
公开(公告)号：US6133129A
公开(公告)日：2000-10-17
申请号：US306875
申请日：1999-05-07
申请人： Qi Xiang , Scott A. Bell , Chih-Yuh Yang
发明人： Qi Xiang , Scott A. Bell , Chih-Yuh Yang
IPC分类号： H01L21/28 , H01L21/321 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28123 , H01L21/28079 , H01L21/321 , H01L29/66575 , Y10S438/947
摘要： A metal structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a base metal structure on a semiconductor substrate. The base metal structure has a first predetermined length defined by sidewalls on ends of the first predetermined length of the base metal structure. The present invention also includes the step of depositing a layer of silicon on the sidewalls of the base metal structure, and this layer of silicon has a predetermined thickness. The layer of silicon reacts with the base metal structure at the sidewalls of the base metal structure in a silicidation anneal to form metal silicide comprised of the layer of silicon that has reacted with the base metal structure at the sidewalls of the base metal structure. The base metal structure has a second predetermined length that is reduced from the first predetermined length when the layer of silicon has consumed into the sidewalls of the base metal structure after the silicidation anneal. The second predetermined length depends on the predetermined thickness of the layer of silicon deposited on the sidewalls of the base metal structure before the silicidation anneal. After the silicidation anneal, the metal silicide is then removed from the sidewalls of the base metal structure. A remaining portion of the base metal structure, after the metal silicide is removed, forms the metal structure of the present invention having the reduced length that is substantially equal to the second predetermined length. The present invention may be used to particular advantage when the metal structure having the reduced length forms a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
摘要翻译：通过使用硅化退火来控制缩短的长度，制造出具有减小的长度的金属结构，其超过了通过光刻可以实现的结构。通常，本发明包括在半导体衬底上形成贱金属结构的步骤。贱金属结构具有由基体金属结构的第一预定长度的端部上的侧壁限定的第一预定长度。本发明还包括在基底金属结构的侧壁上沉积硅层的步骤，并且该硅层具有预定的厚度。硅层在贱金属结构的侧壁处与基体金属结构反应，以在硅化退火中形成金属硅化物，该金属硅化物由在贱金属结构的侧壁处与基体金属结构反应的硅层组成。贱金属结构具有第二预定长度，当硅层在硅化退火之后消耗到基体金属结构的侧壁中时，该第一预定长度从第一预定长度减小。第二预定长度取决于在硅化退火之前沉积在贱金属结构的侧壁上的硅层的预定厚度。在硅化退火之后，然后从基体金属结构的侧壁去除金属硅化物。在金属硅化物被除去之后，母体金属结构的剩余部分形成具有基本上等于第二预定长度的减小的长度的本发明的金属结构。当具有减小的长度的金属结构形成MOSFET（金属氧化物半导体场效应晶体管）的栅电极时，本发明可以被用于特别的优点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式