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1. 发明授权

US5990524A Silicon oxime spacer for preventing over-etching during local interconnect formation 失效
标题翻译：硅肟间隔物，用于在局部互连形成期间防止过蚀刻
公开(公告)号：US5990524A
公开(公告)日：1999-11-23
申请号：US993868
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L21/768 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76895
摘要： During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. Improved, multipurpose spacers are provided to reduce the chances of over-etching. The multipurpose spacers are made of silicon oxime. The etching plasmas that are used to etch one or more overlying dielectric layers tend to have a higher selectivity ratio to the multipurpose spacers than to the conventional oxide spacers. Additionally, the multipurpose spacers do not tend to degrade the hot carrier injection (HCI) properties as would a typical nitride spacer.
摘要翻译：在半导体晶片中局部互连的镶嵌形成期间，由于将与晶体管栅极相邻的氧化物间隔物暴露于用于蚀刻一个或多个蚀刻等离子体的一个或多个蚀刻等离子体，可以将穿透区域形成为衬底，更重叠的电介质层。穿通区域可能会损坏晶体管电路。提供改进的多用途间隔件以减少过度蚀刻的机会。多用途间隔件由硅肟制成。用于蚀刻一个或多个上覆电介质层的蚀刻等离子体与常规氧化物间隔物相比往往具有比多用途间隔物更高的选择比。此外，多用途间隔物不会像典型的氮化物间隔物一样降低热载流子注入（HCl）性质。

2. 发明授权

US6103611A Methods and arrangements for improved spacer formation within a semiconductor device 失效
标题翻译：用于改善半导体器件内的间隔物形成的方法和布置
公开(公告)号：US6103611A
公开(公告)日：2000-08-15
申请号：US993830
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L21/311 , H01L21/00 , H01L21/3065
CPC分类号： H01L21/31116
摘要： Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
摘要翻译：提供了在半导体器件内形成间隔物期间增加工艺控制的方法和装置。这些方法和布置包括使用非功能或虚拟线，区域和/或图案来创建导致随后形成的间隔物在形状和尺寸上更可预测和均匀的拓扑。

3. 发明授权

US06380588B1 Semiconductor device having uniform spacers 有权
标题翻译：具有均匀间隔物的半导体器件
公开(公告)号：US06380588B1
公开(公告)日：2002-04-30
申请号：US09567013
申请日：2000-05-09
申请人： William G. En , Minh Van Ngo , Chih-Yuk Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuk Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L2100
CPC分类号： H01L21/31116
摘要： A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
摘要翻译：具有功能和非功能或虚拟线，区域和/或图案的半导体器件，以产生导致随后形成的间隔物在形状和尺寸上更可预测和均匀的拓扑。

4. 发明授权

US5963841A Gate pattern formation using a bottom anti-reflective coating 失效
标题翻译：使用底部抗反射涂层的栅格图案形成
公开(公告)号：US5963841A
公开(公告)日：1999-10-05
申请号：US924370
申请日：1997-09-05
申请人： Olov B. Karlsson , Christopher F. Lyons , Minh Van Ngo , Scott A. Bell , David K. Foote
发明人： Olov B. Karlsson , Christopher F. Lyons , Minh Van Ngo , Scott A. Bell , David K. Foote
IPC分类号： H01L21/3213 , H01L21/302
CPC分类号： H01L21/32139
摘要： A gate is formed on a semiconductor substrate by using a bottom anti-reflective coating (BARC) to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, a SiON BARC over the conductive layer, a thin oxide film over the SiON BARC. The resist mask is formed on the oxide film. The SiON BARC improves the resist mask formation process. The wafer stack is then shaped to form one or more polysilicon gates by sequentially etching through selected portions of the oxide film, the BARC, and the gate conductive layer as defined by the etch windows in the resist mask. Once properly shaped, the remaining portions of the resist mask, oxide film and SiON BARC are removed.
摘要翻译：通过使用底部抗反射涂层（BARC）在半导体衬底上形成栅极以更好地控制通过形成在其上的深UV抗蚀剂掩模所限定的栅极的临界尺寸（CD）。晶片堆叠包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅栅极层，导电层上的SiON BARC，SiON BARC上的薄氧化物膜。在氧化物膜上形成抗蚀剂掩模。 SiON BARC改进了抗蚀剂掩模形成过程。然后通过依次蚀刻通过抗蚀剂掩模中由蚀刻窗口限定的氧化膜，BARC和栅极导电层的选定部分，将晶片堆叠成形以形成一个或多个多晶硅栅极。一旦适当成形，就去除了抗蚀剂掩模，氧化膜和SiON BARC的其余部分。

5. 发明授权

US6087271A Methods for removal of an anti-reflective coating following a resist protect etching process 失效
标题翻译：在抗蚀剂保护蚀刻工艺之后去除抗反射涂层的方法
公开(公告)号：US6087271A
公开(公告)日：2000-07-11
申请号：US993869
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Olov B. Karlsson , Christopher F. Lyons , Maria Chow Chan
发明人： William G. En , Minh Van Ngo , Olov B. Karlsson , Christopher F. Lyons , Maria Chow Chan
IPC分类号： H01L21/027 , H01L21/311 , H01L21/336 , H01L21/283
CPC分类号： H01L29/6659 , H01L21/31116 , H01L29/6656 , H01L21/0276 , H01L29/66545
摘要： A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate following at least one etch back process associated with a spacer formation and/or subsequent resistor protect etching process or processes. The method eliminates the need to use HF acid in the stripping process by substantially reducing the thickness of the BARC during each of the etching back processes, such that, only a thin layer of BARC material remains that can be easily removed with phosphoric acid.
摘要翻译：提供了一种用于在与间隔物形成和/或随后的电阻器保护蚀刻工艺或工艺相关联的至少一个回蚀工艺之后从晶体管栅极去除底部抗反射涂层（BARC）的方法。该方法消除了在剥离过程中通过在每次蚀刻回加工过程中通过显着降低BARC的厚度而需要使用HF酸，使得仅剩下可以用磷酸容易地除去的薄的BARC材料层。

6. 发明授权

US6027959A Methods for in-situ removal of an anti-reflective coating during a nitride resistor protect etching process 失效
标题翻译：在氮化物电阻器期间原位去除抗反射涂层的方法保护蚀刻工艺
公开(公告)号：US6027959A
公开(公告)日：2000-02-22
申请号：US993829
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Olov B. Karlsson , Maria Chow Chan
发明人： William G. En , Minh Van Ngo , Olov B. Karlsson , Maria Chow Chan
IPC分类号： H01L21/027 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/335
CPC分类号： H01L29/6659 , H01L21/31116 , H01L29/6656 , H01L21/0276 , H01L21/32139
摘要： A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate during an etch back process associated with a nitride resistor protect etch process. The method includes removing a silicon oxynitride BARC, in-situ, during an oxide resistor protect etching process using a plasma formed with CF.sub.4 gas, CHF.sub.3 gas, O.sub.2 gas, and Argon (Ar) gas.
摘要翻译：提供了一种在与氮化物电阻器保护蚀刻工艺相关的回蚀工艺期间从晶体管栅极去除底部抗反射涂层（BARC）的方法。该方法包括在使用由CF 4气体，CHF 3气体，O 2气体和氩气（Ar）气体形成的等离子体的氧化物电阻保护蚀刻工艺期间原位去除氮氧化硅BARC。

7. 发明授权

US06066567A Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process 失效
标题翻译：在氧化物电阻器保护蚀刻工艺期间原位去除抗反射涂层的方法
公开(公告)号：US06066567A
公开(公告)日：2000-05-23
申请号：US993833
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Olov B. Karlsson
发明人： William G. En , Minh Van Ngo , Olov B. Karlsson
IPC分类号： H01L21/027 , H01L21/311 , H01L27/06 , H01L21/3065
CPC分类号： H01L27/0629 , H01L21/31116 , H01L21/0276 , Y10S438/952
摘要： A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate during the etch back process associated with a resistor protect etch process. The method includes removing a silicon oxynitride BARC, in-situ, during a resistor protect etching process using a plasma formed with CF.sub.4 gas, CHF.sub.3 gas, and Argon (Ar) gas.
摘要翻译：提供了一种用于在与电阻器保护蚀刻工艺相关的回蚀工艺期间从晶体管栅极去除底部抗反射涂层（BARC）的方法。该方法包括在使用由CF 4气体，CHF 3气体和氩气（Ar）气体形成的等离子体的电阻保护蚀刻工艺期间原位去除氮氧化硅BARC。

8. 发明授权

US06867130B1 Enhanced silicidation of polysilicon gate electrodes 有权
标题翻译：增强多晶硅栅电极的硅化
公开(公告)号：US06867130B1
公开(公告)日：2005-03-15
申请号：US10445936
申请日：2003-05-28
申请人： Olov B. Karlsson , Simon S. Chan , William G. En , Mark W. Michael
发明人： Olov B. Karlsson , Simon S. Chan , William G. En , Mark W. Michael
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66507 , H01L21/28114 , H01L21/28518 , H01L29/42376 , H01L29/6659 , H01L29/7833
摘要： Semiconductor devices exhibiting reduced gate resistance and reduced silicide spiking in source/drain regions are fabricated by forming thin metal silicide layers on the gate electrode and source/drain regions and then selectively resilicidizing the gate electrodes. Embodiments include forming the thin metal silicide layers on the polysilicon gate electrodes and source/drain regions, depositing a dielectric gap filling layer, as by high density plasma deposition, etching back to selectively expose the silicidized polysilicon gate electrodes and resilicidizing the polysilicon gate electrodes to increase the thickness of the metal silicide layers thereon. Embodiments further include resilicidizing the polysilicon gate electrodes including a portion of the upper side surfaces forming mushroom shaped metal silicide layers.
摘要翻译：通过在栅极电极和源极/漏极区域上形成薄金属硅化物层，然后选择性地使栅电极重新硅化，来制造在源极/漏极区域中显示出降低的栅极电阻和减少的硅化物尖峰的半导体器件。实施例包括在多晶硅栅极电极和源极/漏极区域上形成薄金属硅化物层，通过高密度等离子体沉积沉积介电间隙填充层，回蚀刻以选择性地暴露硅化多晶硅栅电极并使多晶硅栅电极重新硅化增加其上的金属硅化物层的厚度。实施例还包括重新硅化多晶硅栅电极，其包括形成蘑菇状金属硅化物层的上侧表面的一部分。

9. 发明申请

US20090256242A1 METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE STORAGE ELEMENT IN A TRENCH OF A WORKPIECE 有权
标题翻译：形成电子装置的方法，包括在工作台的形式中形成充电储存元件
公开(公告)号：US20090256242A1
公开(公告)日：2009-10-15
申请号：US12102488
申请日：2008-04-14
申请人： Suketu Arun Parikh , Olov B. Karlsson , Yu Sun , Shankar Sinha , Timothy Thurgate
发明人： Suketu Arun Parikh , Olov B. Karlsson , Yu Sun , Shankar Sinha , Timothy Thurgate
IPC分类号： H01L21/425 , H01L23/58
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1041 , H01L29/66666 , H01L29/7827
摘要： A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.
摘要翻译：一种形成电子器件的方法，包括在包括衬底的工件中形成第一沟槽，所述第一沟槽具有侧壁和在所述侧壁之间延伸宽度的底表面，并且沿着所述侧壁和底部形成电荷存储层第一沟槽的表面。该方法还包括在第一沟槽的底表面下方的衬底内注入离子以形成植入区域并退火植入区域，其中在退火之后，植入区域延伸底表面的宽度并沿着侧壁的一部分。

10. 发明授权

US06984569B2 Shallow trench isolation (STI) region with high-K liner and method of formation 失效
公开(公告)号：US06984569B2
公开(公告)日：2006-01-10
申请号：US10642916
申请日：2003-08-18
申请人： Olov B. Karlsson , HaiHong Wang , Bin Yu , Zoran Krivokapic , Qi Xiang
发明人： Olov B. Karlsson , HaiHong Wang , Bin Yu , Zoran Krivokapic , Qi Xiang
IPC分类号： H01L21/8224
CPC分类号： H01L29/7842 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78654
摘要： A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

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