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1. 发明授权

US06773998B1 Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning 有权
标题翻译：改进的薄膜堆叠和图案化策略，用于应力补偿和防止无定形碳栅图案中的图案变形
公开(公告)号：US06773998B1
公开(公告)日：2004-08-10
申请号：US10445129
申请日：2003-05-20
申请人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
发明人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21336
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/31116 , H01L21/3146 , H01L21/32137 , H01L21/32139
摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.
摘要翻译：集成电路的方法包括使用无定形碳ARC掩模。一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

2. 发明授权

US06828259B2 Enhanced transistor gate using E-beam radiation 失效
标题翻译：使用电子束辐射的增强型晶体管栅极
公开(公告)号：US06828259B2
公开(公告)日：2004-12-07
申请号：US10017855
申请日：2001-12-14
申请人： Philip A. Fisher , Chih-Yuh Yang , Marina V. Plat , Russell R.A. Callahan , Ashok M. Khathuria
发明人： Philip A. Fisher , Chih-Yuh Yang , Marina V. Plat , Russell R.A. Callahan , Ashok M. Khathuria
IPC分类号： H01L2126
CPC分类号： H01L21/32139 , H01L21/28123
摘要： A process for forming a transistor having a gate width of less than 70 nm is disclosed herein. The process includes E-beam irradiation a gate patterned on a photoresist layer, trimming the gate patterned on the photoresist layer, and etching the gate patterned on the photoresist layer to a polysilicon layer disposed below the photoresist layer.
摘要翻译：本文公开了一种形成栅极宽度小于70nm的晶体管的工艺。该工艺包括在光致抗蚀剂层上图案化的栅极的电子束照射，修整在光致抗蚀剂层上图案化的栅极，以及将在光致抗蚀剂层上图案化的栅极蚀刻到设置在光致抗蚀剂层下方的多晶硅层。

3. 发明授权

US06787476B1 Etch stop layer for etching FinFET gate over a large topography 有权
标题翻译：蚀刻停止层，用于在大地形上蚀刻FinFET栅极
公开(公告)号：US06787476B1
公开(公告)日：2004-09-07
申请号：US10632989
申请日：2003-08-04
申请人： Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Chih-Yuh Yang , Bin Yu
发明人： Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21302
CPC分类号： H01L29/785 , H01L21/31116 , H01L21/31144 , H01L29/4908 , H01L29/66795
摘要： A method of forming a gate for a Fin Field Effect Transistor (FinFET) is provided. The method includes forming a first layer of material over a fin and forming a second layer over the first layer. The second layer includes either Ti or TiN. The method further includes forming a third layer over the second layer. The third layer includes an anti-reflective coating. The method also includes etching the first, second and third layers to form the gate for the FinFET.
摘要翻译：提供了一种形成Fin场效应晶体管（FinFET）的栅极的方法。该方法包括在翅片上形成第一层材料，并在第一层上形成第二层。第二层包括Ti或TiN。该方法还包括在第二层上形成第三层。第三层包括抗反射涂层。该方法还包括蚀刻第一，第二和第三层以形成用于FinFET的栅极。

4. 发明授权

US06960804B1 Semiconductor device having a gate structure surrounding a fin 有权
标题翻译：具有围绕鳍片的栅极结构的半导体器件
公开(公告)号：US06960804B1
公开(公告)日：2005-11-01
申请号：US10633034
申请日：2003-10-10
申请人： Chih-Yuh Yang , Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Bin Yu
发明人： Chih-Yuh Yang , Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Bin Yu
IPC分类号： H01L21/027 , H01L21/336 , H01L29/786 , H01L29/788
CPC分类号： H01L29/785 , H01L21/0276 , H01L29/42392 , H01L29/66795
摘要： A double-semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The gate is formed on the insulating layer and surrounds the top surface, bottom surface and the side surfaces of the fin in the channel region of the semiconductor device. Surrounding the fin with gate material results in an increased total channel width and more flexible device adjustment margins.
摘要翻译：双半导体器件包括衬底，绝缘层，鳍和栅极。绝缘层形成在基板上，并且鳍形成在绝缘层上。翅片具有多个侧表面，顶表面和底表面。栅极形成在绝缘层上并且围绕半导体器件的沟道区域中的鳍的顶表面，底表面和侧表面。用门材料围绕翅片会导致总通道宽度增加和设备调整裕度更灵活。

5. 发明授权

US07915160B1 Methods for forming small contacts 有权
标题翻译：形成小触点的方法
公开(公告)号：US07915160B1
公开(公告)日：2011-03-29
申请号：US11625190
申请日：2007-01-19
申请人： Cyrus E. Tabery , Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
发明人： Cyrus E. Tabery , Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21/4763 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L29/66795 , H01L29/785 , H01L29/7856
摘要： Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.
摘要翻译：提供了用于形成用于半导体器件的触点的方法。所述方法可以包括在半导体器件上沉积诸如多晶硅，氮化物，氧化物和/或碳材料的各种材料。所述方法还可以包括形成接触孔并填充接触孔以形成用于半导体器件的接触。

6. 发明授权

US07183223B1 Methods for forming small contacts 有权
标题翻译：形成小触点的方法
公开(公告)号：US07183223B1
公开(公告)日：2007-02-27
申请号：US10728909
申请日：2003-12-08
申请人： Cyrus E. Tabery , Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
发明人： Cyrus E. Tabery , Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L29/66795 , H01L29/785 , H01L29/7856
摘要： Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.
摘要翻译：提供了用于形成用于半导体器件的触点的方法。所述方法可以包括在半导体器件上沉积诸如多晶硅，氮化物，氧化物和/或碳材料的各种材料。所述方法还可以包括形成接触孔并填充接触孔以形成用于半导体器件的接触。

7. 发明授权

US07005386B1 Method for reducing resist height erosion in a gate etch process 有权
标题翻译：在栅极蚀刻工艺中降低抗蚀剂高度腐蚀的方法
公开(公告)号：US07005386B1
公开(公告)日：2006-02-28
申请号：US10656467
申请日：2003-09-05
申请人： Scott Bell , Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Ashok M. Khathuria
发明人： Scott Bell , Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Ashok M. Khathuria
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0274 , H01L21/31058
摘要： According to one exemplary embodiment, a method for reducing resist height erosion in a gate etch process comprises a step of forming a first resist mask on an anti-reflective coating layer situated over a substrate, where the first resist mask has a first width. The anti-reflective coating layer may be, for example, an organic material. The method further comprises a step of trimming the first resist mask to form a second resist mask, where the second resist mask has a second width, and where the second width is less than the first width. The step of trimming the first resist mask may further comprise, for example, etching the anti-reflective coating layer. According to this exemplary embodiment, the method further comprises a step of performing an HBr plasma treatment on the second resist mask, wherein the HBr plasma treatment causes a vertical etch rate of the second resist mask to decrease.
摘要翻译：根据一个示例性实施例，用于降低栅极蚀刻工艺中的抗蚀剂高度腐蚀的方法包括在位于衬底上的抗反射涂层上形成第一抗蚀剂掩模的步骤，其中第一抗蚀剂掩模具有第一宽度。抗反射涂层可以是例如有机材料。该方法还包括修整第一抗蚀剂掩模以形成第二抗蚀剂掩模的步骤，其中第二抗蚀剂掩模具有第二宽度，并且其中第二宽度小于第一宽度。修整第一抗蚀剂掩模的步骤还可以包括例如蚀刻抗反射涂层。根据该示例性实施例，该方法还包括在第二抗蚀剂掩模上执行HBr等离子体处理的步骤，其中HBr等离子体处理导致第二抗蚀剂掩模的垂直蚀刻速率降低。

8. 发明授权

US6103611A Methods and arrangements for improved spacer formation within a semiconductor device 失效
标题翻译：用于改善半导体器件内的间隔物形成的方法和布置
公开(公告)号：US6103611A
公开(公告)日：2000-08-15
申请号：US993830
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L21/311 , H01L21/00 , H01L21/3065
CPC分类号： H01L21/31116
摘要： Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
摘要翻译：提供了在半导体器件内形成间隔物期间增加工艺控制的方法和装置。这些方法和布置包括使用非功能或虚拟线，区域和/或图案来创建导致随后形成的间隔物在形状和尺寸上更可预测和均匀的拓扑。

9. 发明授权

US5990524A Silicon oxime spacer for preventing over-etching during local interconnect formation 失效
标题翻译：硅肟间隔物，用于在局部互连形成期间防止过蚀刻
公开(公告)号：US5990524A
公开(公告)日：1999-11-23
申请号：US993868
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L21/768 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76895
摘要： During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. Improved, multipurpose spacers are provided to reduce the chances of over-etching. The multipurpose spacers are made of silicon oxime. The etching plasmas that are used to etch one or more overlying dielectric layers tend to have a higher selectivity ratio to the multipurpose spacers than to the conventional oxide spacers. Additionally, the multipurpose spacers do not tend to degrade the hot carrier injection (HCI) properties as would a typical nitride spacer.
摘要翻译：在半导体晶片中局部互连的镶嵌形成期间，由于将与晶体管栅极相邻的氧化物间隔物暴露于用于蚀刻一个或多个蚀刻等离子体的一个或多个蚀刻等离子体，可以将穿透区域形成为衬底，更重叠的电介质层。穿通区域可能会损坏晶体管电路。提供改进的多用途间隔件以减少过度蚀刻的机会。多用途间隔件由硅肟制成。用于蚀刻一个或多个上覆电介质层的蚀刻等离子体与常规氧化物间隔物相比往往具有比多用途间隔物更高的选择比。此外，多用途间隔物不会像典型的氮化物间隔物一样降低热载流子注入（HCl）性质。

10. 发明授权

US07183152B1 Epitaxially grown fin for FinFET 有权
标题翻译： FinFET的外延生长鳍
公开(公告)号：US07183152B1
公开(公告)日：2007-02-27
申请号：US10975475
申请日：2004-10-29
申请人： Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
发明人： Srikanteswara Dakshina-Murthy , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/00 , H01L21/84 , H01L21/3205
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66795 , H01L29/78687
摘要： A method of forming a fin for a fin field effect transistor (FinFET) includes defining a trench in a layer of first material, where a width of an opening of the trench is substantially smaller than a thickness of the layer. The method includes growing a second material in the trench to form the fin and removing the layer of first material.
摘要翻译：形成鳍状场效应晶体管（FinFET）的鳍片的方法包括在第一材料层中限定沟槽，其中沟槽的开口的宽度基本上小于该层的厚度。该方法包括在沟槽中生长第二材料以形成翅片并去除第一材料层。

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