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41. 发明授权

US08495310B2 Method and system including plural memory controllers and a memory access control bus for accessing a memory device 有权
标题翻译：包括多个存储器控制器和用于访问存储器件的存储器访问控制总线的方法和系统
公开(公告)号：US08495310B2
公开(公告)日：2013-07-23
申请号：US12235063
申请日：2008-09-22
申请人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
发明人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
IPC分类号： G06F13/36 , G06F13/16
CPC分类号： G06F13/1605 , G06F13/1684 , Y02D10/14
摘要： A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.
摘要翻译：系统和方法利用可以经由存储器件的相应端口被多个控制器或处理器核心访问的存储器件。每个控制器可以经由数据总线耦合到存储器设备的相应端口。存储器设备的每个端口可以与存储器的预定义部分相关联，从而使每个控制器访问不同部分的存储器，而不受其他控制器的干扰。公共命令/地址总线可以将多个控制器耦合到存储器设备。每个控制器可以在存储器访问控制总线上断言有效信号以获得对命令/地址总线的访问以启动存储器访问。在一些实施例中，多个存储器件可以以堆叠的存储器配置布置在存储器封装中。

42. 发明申请

US20090271678A1 INTERFACE VOLTAGE ADJUSTMENT BASED ON ERROR DETECTION 有权
标题翻译：基于错误检测的接口电压调整
公开(公告)号：US20090271678A1
公开(公告)日：2009-10-29
申请号：US12109826
申请日：2008-04-25
申请人： Andreas Schneider , Markus Balb , Thomas Hein , Christoph Bilger , Martin Brox , Peter Gregorius , Michael Richter
发明人： Andreas Schneider , Markus Balb , Thomas Hein , Christoph Bilger , Martin Brox , Peter Gregorius , Michael Richter
IPC分类号： H03M13/00 , G06F11/07
CPC分类号： G11C29/021 , G06F11/1004 , G11C7/1006 , G11C11/401 , G11C11/4074 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/028 , G11C2029/0411 , H03M13/03
摘要： A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.
摘要翻译：调整接口电压的方法包括在存储器件和控制器之间传输数据，以及检测数据传输中是否发生错误。基于检测来调整存储器件和控制器中的至少一个的接口电压。

43. 发明申请

US20090039529A1 Integrated Circuit Having a Plurality of Connection Pads and Integrated Circuit Package 审中-公开
标题翻译：具有多个连接焊盘和集成电路封装的集成电路
公开(公告)号：US20090039529A1
公开(公告)日：2009-02-12
申请号：US11835967
申请日：2007-08-08
申请人： Sebastian Mueller , Thomas Hein
发明人： Sebastian Mueller , Thomas Hein
IPC分类号： H01L23/48 , H01L21/02
CPC分类号： H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/73 , H01L24/91 , H01L2224/16 , H01L2224/48227 , H01L2224/4824 , H01L2924/00014 , H01L2924/01033 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In accordance with an embodiment of the invention, an integrated circuit including a plurality of connection pads is provided, wherein a first connection pad is configured in accordance with a first contacting technology, and wherein a second connection pad is configured in accordance with a second contacting technology. The second contacting technology is different from the first contacting technology.
摘要翻译：根据本发明的实施例，提供了包括多个连接焊盘的集成电路，其中根据第一接触技术配置第一连接焊盘，并且其中第二连接焊盘根据第二接触技术。第二接触技术与第一接触技术不同。

44. 发明申请

US20080189481A1 METHODS AND SYSTEMS FOR STORING DATA BASED ON A RELIABILITY REQUIREMENT 审中-公开
标题翻译：基于可靠性要求存储数据的方法和系统
公开(公告)号：US20080189481A1
公开(公告)日：2008-08-07
申请号：US11672427
申请日：2007-02-07
申请人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
发明人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
IPC分类号： G06F12/00
CPC分类号： G06F12/0223 , G06F11/1008
摘要： Methods and apparatus for storing data in different regions of the memory device based on, for example, a reliability requirement of the data. A memory controller may determine a category for data, for example, high reliability data and low reliability data, prior to storing the data in memory. The data may be stored in a region of memory associated with the category of data according to a method associated with the category of data. For example, high reliability data may be stored in a particular region of memory using lower clock frequencies, with additional error correction bits, and/or at multiple redundant locations. In contrast, low reliability data may be stored other regions of the memory using higher clock frequencies, without additional error correction bits and/or at singular locations (i.e., without redundant locations.
摘要翻译：基于例如数据的可靠性要求，在存储装置的不同区域中存储数据的方法和装置。在将数据存储在存储器中之前，存储器控制器可以确定用于数据的类别，例如高可靠性数据和低可靠性数据。可以根据与数据类别相关联的方法将数据存储在与数据类别相关联的存储器的区域中。例如，高可靠性数据可以使用更低的时钟频率，附加的纠错位和/或在多个冗余位置存储在存储器的特定区域中。相比之下，低可靠性数据可以使用更高的时钟频率存储在存储器的其他区域中，而不需要额外的纠错位和/或在单个位置（即，没有冗余位置）。

45. 发明申请

US20080115030A1 Information transmission and reception 有权
标题翻译：信息发送和接收
公开(公告)号：US20080115030A1
公开(公告)日：2008-05-15
申请号：US11599992
申请日：2006-11-15
申请人： Thomas Hein , Rex Kho , Aaron John Nygren
发明人： Thomas Hein , Rex Kho , Aaron John Nygren
IPC分类号： H03M13/03
CPC分类号： H03M5/145
摘要： An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information. Accordingly, an information receiving apparatus comprises an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.
摘要翻译：描述信息发送装置。接口包括用于有效数据字的第一输入，用于要发送的信息的第二输入和输出，其中接口提供数据字或在输出端可被识别为无效数据字的数据字，这取决于信息。因此，信息接收装置包括包括用于数据字的输入和用于信息的输出的接口，其中接口根据数据字是有效数据字还是无效数据字导出信息。

46. 发明申请

US20080008023A1 Memory device, and method for operating a memory device 有权
标题翻译：存储器件和操作存储器件的方法
公开(公告)号：US20080008023A1
公开(公告)日：2008-01-10
申请号：US11481157
申请日：2006-07-05
申请人： Martin Brox , Thomas Hein
发明人： Martin Brox , Thomas Hein
IPC分类号： G11C8/00
CPC分类号： G11C29/26 , G11C11/4087 , G11C29/1201 , G11C29/46
摘要： A memory device, in particular to a DRAM, and a system comprising a memory device is disclosed. Further, the invention relates to a method for operating a memory device. According to an embodiment of the invention, a memory device is provided, including: a first chip select pin, and a second chip select pin. Further, a method for operating a memory device is provided, the memory device including a first chip select pin, and a second chip select pin, the method including: applying a chip select signal to the first or the second chip select pin.
摘要翻译：公开了一种存储器件，特别是DRAM，以及包括存储器件的系统。此外，本发明涉及一种用于操作存储器件的方法。根据本发明的一个实施例，提供了一种存储器件，包括：第一芯片选择引脚和第二芯片选择引脚。此外，提供了一种用于操作存储器件的方法，所述存储器件包括第一芯片选择引脚和第二芯片选择引脚，所述方法包括：将片选信号施加到第一芯片选择引脚或第二芯片选择引脚。

47. 发明申请

US20070283297A1 Signal processing circuit 审中-公开
标题翻译：信号处理电路
公开(公告)号：US20070283297A1
公开(公告)日：2007-12-06
申请号：US11443491
申请日：2006-05-30
申请人： Thomas Hein , Rex Kho
发明人： Thomas Hein , Rex Kho
IPC分类号： G06F17/50
CPC分类号： G11C7/22 , G11C7/222 , H04L7/02 , H04L7/0331
摘要： A signal processing circuit includes a first circuit including a first clock signal generator with an output for a first clock signal and a second clock signal generator with an output for a second clock signal and an input for a comparison signal. The second clock signal is generated by the second clock signal generator based on the comparison signal. A second circuit includes a phase detector with a first input for the first clock signal, with a second input for the second clock signal and an output for the comparison signal indicating a relation between the phases of the first clock signal received at the first input and the second clock signal received at the second input.
摘要翻译：信号处理电路包括：第一电路，包括具有用于第一时钟信号的输出的第一时钟信号发生器和具有用于第二时钟信号的输出和用于比较信号的输入的第二时钟信号发生器。第二时钟信号由第二时钟信号发生器基于比较信号产生。第二电路包括具有用于第一时钟信号的第一输入的相位检测器，具有用于第二时钟信号的第二输入和用于比较信号的输出，该输出指示在第一输入处接收到的第一时钟信号的相位之间的关系;以及在第二输入处接收的第二时钟信号。

48. 发明申请

US20070247989A1 Integrated semiconductor memory with generation of data 有权
标题翻译：具有生成数据的集成半导体存储器
公开(公告)号：US20070247989A1
公开(公告)日：2007-10-25
申请号：US11731763
申请日：2007-03-30
申请人： Thomas Hein
发明人： Thomas Hein
IPC分类号： G11B20/10
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/1051 , G11C7/1069
摘要： An integrated semiconductor memory with generation of data comprises a clock connection to apply a clock signal, a memory cell array with memory cells to store data of a first data record and a data generator circuit with a first input connection to apply the data of the first data record, with a first output connection to output data of a second data record, and with a second output connection to generate a first control signal. The data generator circuit includes an evaluation unit whose input is supplied with the first data record, the second data record and a second control signal, the second control signal being delayed by one clock period of the clock signal with respect to the first control signal. The data generator circuit is adapted to generate the data values of the data of the second data record in dependence on the evaluation of the data values of the first and second data record and the second control signal.
摘要翻译：具有数据生成的集成半导体存储器包括用于施加时钟信号的时钟连接，具有存储单元的存储单元阵列以存储第一数据记录的数据和具有第一输入连接的数据发生器电路，以将第一数据记录，具有第一输出连接以输出第二数据记录的数据，并具有第二输出连接以产生第一控制信号。数据发生器电路包括评估单元，其输入被提供有第一数据记录，第二数据记录和第二控制信号，第二控制信号被延迟相对于第一控制信号的时钟信号的一个时钟周期。数据发生器电路适于根据对第一和第二数据记录和第二控制信号的数据值的评估来产生第二数据记录的数据的数据值。

49. 发明申请

US20070006057A1 Semiconductor memory chip and method of protecting a memory core thereof 审中-公开
标题翻译：半导体存储器芯片及其存储器核心的保护方法
公开(公告)号：US20070006057A1
公开(公告)日：2007-01-04
申请号：US11171585
申请日：2005-06-30
申请人： Paul Wallner , Andre Schaefer , Thomas Hein , Peter Gregorius
发明人： Paul Wallner , Andre Schaefer , Thomas Hein , Peter Gregorius
IPC分类号： G11C29/00
CPC分类号： G11C7/1006
摘要： Provided is a semiconductor memory chip that includes a memory core and an interface circuit having decoding, selecting and scheduling circuit means for decoding from a signal frame a respective type of data signals, command signals and address signals, selection of actions which are required in the memory chip according to the respective signal type and scheduling the memory core and sections of the interface circuit respectively for the decoded signal. The interface circuit further comprises a CRC bit decoding and check unit and a protection circuit arranged for protecting the memory core and for enabling/disabling switching through of signal transfer from the interface circuit to the memory core depending on a correct/incorrect signal generated by the CRC bit decoding and check unit according to the result of checking an information within the frame by means of the CRC bits which are inserted in a signal frame in association to the respective information in accordance with a defined transmission protocol.
摘要翻译：提供了一种半导体存储器芯片，其包括存储器核心和具有解码，选择和调度电路装置的接口电路，用于从信号帧解码相应类型的数据信号，命令信号和地址信号，选择所需的动作存储器芯片，分别对接收电路的存储器核心部分和解码信号进行调度。接口电路还包括CRC位解码和校验单元以及保护电路，该保护电路用于保护存储器核心并根据由该接口电路产生的正确/不正确的信号来允许/禁止从接口电路到存储器核心的信号传输切换 CRC比特解码和校验单元根据通过根据定义的传输协议与插入到信号帧中的各个信息相关联的CRC比特来检查帧内的信息的结果。

50. 发明授权

US07156463B2 Motor vehicle seat 失效
标题翻译：汽车座椅
公开(公告)号：US07156463B2
公开(公告)日：2007-01-02
申请号：US10487539
申请日：2002-08-30
申请人： Werner Taubmann , Thomas Hein
发明人： Werner Taubmann , Thomas Hein
IPC分类号： B60N2/02
CPC分类号： B60N2/045 , B60N2/20
摘要： A motor vehicle seat has a pivoted backrest that can be swung forward in the direction of a seating of the seat, a longitudinal seat adjuster for adjusting the longitudinal position of the seat, a locking device of the longitudinal seat adjuster for locking a longitudinal seat position previously adjusted, and an unlocking mechanism for unlocking the locking device, and a flexible traction device via which the unlocking mechanism is coupled with the backrest so that the locking device is unlocked when the backrest is swung forward. An actuation element acts upon the traction device with a force component at an angle to the direction of extension of the traction device when the backrest is swung forward, thereby tightening the traction device and unlocking the locking device.
摘要翻译：机动车辆座椅具有枢转的靠背，其可以沿着座椅的座椅的方向向前摆动，用于调节座椅的纵向位置的纵向座椅调节器，用于锁定纵向座椅位置的纵向座椅调节器的锁定装置以及用于解锁锁定装置的解锁机构，以及柔性牵引装置，解锁机构通过该解锁装置与靠背联接，使得当靠背向前摆动时锁定装置解锁。当靠背向前摆动时，致动元件以牵引装置的延伸方向成角度地作用在牵引装置上，由此紧固牵引装置并解锁锁定装置。

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