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1. 发明授权

US08495310B2 Method and system including plural memory controllers and a memory access control bus for accessing a memory device 有权
标题翻译：包括多个存储器控制器和用于访问存储器件的存储器访问控制总线的方法和系统
公开(公告)号：US08495310B2
公开(公告)日：2013-07-23
申请号：US12235063
申请日：2008-09-22
申请人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
发明人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
IPC分类号： G06F13/36 , G06F13/16
CPC分类号： G06F13/1605 , G06F13/1684 , Y02D10/14
摘要： A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.
摘要翻译：系统和方法利用可以经由存储器件的相应端口被多个控制器或处理器核心访问的存储器件。每个控制器可以经由数据总线耦合到存储器设备的相应端口。存储器设备的每个端口可以与存储器的预定义部分相关联，从而使每个控制器访问不同部分的存储器，而不受其他控制器的干扰。公共命令/地址总线可以将多个控制器耦合到存储器设备。每个控制器可以在存储器访问控制总线上断言有效信号以获得对命令/地址总线的访问以启动存储器访问。在一些实施例中，多个存储器件可以以堆叠的存储器配置布置在存储器封装中。

2. 发明申请

US20100077157A1 MULTI MASTER DRAM ARCHITECTURE 有权
标题翻译：多主体DRAM架构
公开(公告)号：US20100077157A1
公开(公告)日：2010-03-25
申请号：US12235063
申请日：2008-09-22
申请人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
发明人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
IPC分类号： G06F12/00 , G06F13/14
CPC分类号： G06F13/1605 , G06F13/1684 , Y02D10/14
摘要： Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, the memory device may be a package comprising a plurality of stacked memory dies.
摘要翻译：本发明的实施例提供一种存储器件，其可以经由存储器件的相应端口被多个控制器或处理器核存取。每个控制器可以经由数据总线耦合到存储器设备的相应端口。存储器设备的每个端口可以与存储器的预定义部分相关联，从而使每个控制器访问不同部分的存储器，而不受其他控制器的干扰。公共命令/地址总线可以将多个控制器耦合到存储器设备。每个控制器可以在存储器访问控制总线上断言有效信号以获得对命令/地址总线的访问以启动存储器访问。在一些实施例中，存储器件可以是包括多个堆叠的存储器管芯的封装。

3. 发明授权

US08914589B2 Multi-port DRAM architecture for accessing different memory partitions 有权
标题翻译：用于访问不同内存分区的多端口DRAM架构
公开(公告)号：US08914589B2
公开(公告)日：2014-12-16
申请号：US12235396
申请日：2008-09-22
申请人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
发明人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
IPC分类号： G06F13/00 , G06F13/16 , G06F12/02
CPC分类号： G06F13/1663 , G06F12/0223 , G06F12/0284 , G06F13/1657 , G06F13/1684 , Y02D10/14
摘要： Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.
摘要翻译：本发明的实施例提供一种存储器件，其可以经由存储器件的相应端口被多个控制器或处理器核存取。每个控制器可以经由数据总线耦合到存储器设备的相应端口。存储器设备的每个端口可以与存储器的预定义部分相关联，从而使每个控制器访问不同部分的存储器，而不受其他控制器的干扰。公共命令/地址总线可以将多个控制器耦合到存储器设备。每个控制器可以在存储器访问控制总线上断言有效信号以获得对命令/地址总线的访问以启动存储器访问。

4. 发明申请

US20080025128A1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US20080025128A1
公开(公告)日：2008-01-31
申请号：US11495689
申请日：2006-07-31
申请人： Jong-Hoon Oh , Ralf Schedel
发明人： Jong-Hoon Oh , Ralf Schedel
IPC分类号： G11C8/00
CPC分类号： G11C7/20 , G11C7/22
摘要： A device or method for activating a memory, which includes receiving a select signal at the memory, receiving a plurality of address bits at the memory, determining whether the select signal is active, determining whether a first bit in the plurality of address bits has a first value, and activating the memory only if the select is active and the first bit has the first value.
摘要翻译：一种用于激活存储器的装置或方法，包括在存储器处接收选择信号，在存储器处接收多个地址位，确定选择信号是否有效，确定多个地址位中的第一位是否具有第一个值，并且只有在select处于活动状态且第一个位具有第一个值时才激活该存储器。

5. 发明授权

US07434018B2 Memory system 有权
公开(公告)号：US07434018B2
公开(公告)日：2008-10-07
申请号：US11495689
申请日：2006-07-31
申请人： Jong-Hoon Oh , Ralf Schedel
发明人： Jong-Hoon Oh , Ralf Schedel
IPC分类号： G06F12/00
CPC分类号： G11C7/20 , G11C7/22
摘要： A device or method for activating a memory, which includes receiving a select signal at the memory, receiving a plurality of address bits at the memory, determining whether the select signal is active, determining whether a first bit in the plurality of address bits has a first value, and activating the memory only if the select is active and the first bit has the first value.

6. 发明授权

US06990159B1 Circuit for generating clock pulses in a communications system 有权
标题翻译：用于在通信系统中产生时钟脉冲的电路
公开(公告)号：US06990159B1
公开(公告)日：2006-01-24
申请号：US10019885
申请日：2000-05-29
申请人： Markus Balb , Ralf Schedel , Walter Fiessinger
发明人： Markus Balb , Ralf Schedel , Walter Fiessinger
IPC分类号： H04L7/00
CPC分类号： H04J3/0688 , H04Q11/0471 , H04Q2213/1305 , H04Q2213/13202 , H04Q2213/13209 , H04Q2213/13214 , H04Q2213/13299 , H04Q2213/1336
摘要： A circuit arrangement for a communication system for terminating a plurality of interfaces at a common bus and for generating a synchronization clock for synchronizing the bus is provided. In one aspect, a circuit arrangement for a communication system includes a first multiplexer controlled by a first control signal with a plurality of inputs corresponding to a plurality of transmission lines of the interfaces, a respective phase control unit, preceding each input of the first multiplexer, which derives a respective clock generator signal from a received signal of the corresponding transmission line, where the clock generator signal of one of the transmission lines is switched through as output signal of the first multiplexer in dependence on the first control signal, and a phase locked loop, at the inputs of which the output signal of the first multiplexer and a clock from a clock generator operated with an external crystal oscillator.
摘要翻译：提供了一种用于在公共总线处终止多个接口并用于生成用于同步总线的同步时钟的通信系统的电路装置。在一个方面，一种用于通信系统的电路装置包括：第一多路复用器，由第一控制信号控制，第一控制信号具有对应于接口的多个传输线的多个输入;相应的相位控制单元，在第一多路复用器的每个输入之前，其根据相应的传输线的接收信号导出相应的时钟发生器信号，其中传输线之一的时钟发生器信号根据第一控制信号被切换为第一多路复用器的输出信号，相位在其输入端，第一多路复用器的输出信号和来自时钟发生器的时钟由外部晶体振荡器操作。

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