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1. 发明申请

US20070091711A1 Method of transferring signals between a memory device and a memory controller 有权
标题翻译：在存储器件和存储器控制器之间传送信号的方法
公开(公告)号：US20070091711A1
公开(公告)日：2007-04-26
申请号：US11259376
申请日：2005-10-26
申请人： Paul Wallner , Andre Schaefer , Thomas Hein , Peter Gregorius
发明人： Paul Wallner , Andre Schaefer , Thomas Hein , Peter Gregorius
IPC分类号： G11C8/00
CPC分类号： G11C8/18
摘要： Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.
摘要翻译：用于从存储器设备到存储器控制器的通信（例如，发送和/或接收）命令，地址和数据信号的方法和装置，反之亦然。数据信号以第一速率传送，命令信号和/或地址信号以低于第一速率的第二速率传送。附加地或替代地，从预定义的命令序列组识别命令序列的命令序列代码以第一速率或第二速率传送。

2. 发明授权

US07587655B2 Method of transferring signals between a memory device and a memory controller 有权
标题翻译：在存储器件和存储器控制器之间传送信号的方法
公开(公告)号：US07587655B2
公开(公告)日：2009-09-08
申请号：US11259376
申请日：2005-10-26
申请人： Paul Wallner , Andre Schaefer , Thomas Hein , Peter Gregorius
发明人： Paul Wallner , Andre Schaefer , Thomas Hein , Peter Gregorius
IPC分类号： G11C29/00
CPC分类号： G11C8/18
摘要： Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first rate. Additionally or alternatively a command sequence code identifying a command sequence from a predefined group of command sequences is transferred with the first or with the second rate.
摘要翻译：用于从存储器设备到存储器控制器的通信（例如，发送和/或接收）命令，地址和数据信号的方法和装置，反之亦然。数据信号以第一速率传送，命令信号和/或地址信号以低于第一速率的第二速率传送。附加地或替代地，从预定义的命令序列组识别命令序列的命令序列代码以第一速率或第二速率传送。

3. 发明申请

US20070006057A1 Semiconductor memory chip and method of protecting a memory core thereof 审中-公开
标题翻译：半导体存储器芯片及其存储器核心的保护方法
公开(公告)号：US20070006057A1
公开(公告)日：2007-01-04
申请号：US11171585
申请日：2005-06-30
申请人： Paul Wallner , Andre Schaefer , Thomas Hein , Peter Gregorius
发明人： Paul Wallner , Andre Schaefer , Thomas Hein , Peter Gregorius
IPC分类号： G11C29/00
CPC分类号： G11C7/1006
摘要： Provided is a semiconductor memory chip that includes a memory core and an interface circuit having decoding, selecting and scheduling circuit means for decoding from a signal frame a respective type of data signals, command signals and address signals, selection of actions which are required in the memory chip according to the respective signal type and scheduling the memory core and sections of the interface circuit respectively for the decoded signal. The interface circuit further comprises a CRC bit decoding and check unit and a protection circuit arranged for protecting the memory core and for enabling/disabling switching through of signal transfer from the interface circuit to the memory core depending on a correct/incorrect signal generated by the CRC bit decoding and check unit according to the result of checking an information within the frame by means of the CRC bits which are inserted in a signal frame in association to the respective information in accordance with a defined transmission protocol.
摘要翻译：提供了一种半导体存储器芯片，其包括存储器核心和具有解码，选择和调度电路装置的接口电路，用于从信号帧解码相应类型的数据信号，命令信号和地址信号，选择所需的动作存储器芯片，分别对接收电路的存储器核心部分和解码信号进行调度。接口电路还包括CRC位解码和校验单元以及保护电路，该保护电路用于保护存储器核心并根据由该接口电路产生的正确/不正确的信号来允许/禁止从接口电路到存储器核心的信号传输切换 CRC比特解码和校验单元根据通过根据定义的传输协议与插入到信号帧中的各个信息相关联的CRC比特来检查帧内的信息的结果。

4. 发明申请

US20070061494A1 Semiconductor memory system, semiconductor memory chip, and method of masking write data in a semiconductor memory chip 审中-公开
标题翻译：半导体存储器系统，半导体存储器芯片以及掩模半导体存储器芯片中的写入数据的方法
公开(公告)号：US20070061494A1
公开(公告)日：2007-03-15
申请号：US11214068
申请日：2005-08-30
申请人： Paul Wallner , Andre Schaefer , Thomas Hein
发明人： Paul Wallner , Andre Schaefer , Thomas Hein
IPC分类号： G06F5/00
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1084
摘要： In a semiconductor memory chips, a semiconductor memory system, and a method of masking write data, data, command, and address signal streams are serially transmitted in the form of signal frames in accordance with a predefined protocol. The semiconductor memory system and predefined protocol are adapted to transfer write data mask bits in a close relation to respectively associated write data units within one write data/command stream. An interface section between a reception interface and a memory core of the semiconductor memory chip includes a frame decoder and a intermediate data buffer.
摘要翻译：在半导体存储器芯片中，半导体存储器系统以及屏蔽写入数据，数据，命令和地址信号流的方法根据预定义的协议以信号帧的形式被串行发送。半导体存储器系统和预定义协议适于将一个写入数据/命令流内的分别关联的写入数据单元的写入数据掩码位传送到紧密关系。半导体存储器芯片的接收接口和存储器核心之间的接口部分包括帧解码器和中间数据缓冲器。

5. 发明授权

US07355921B2 Device in a memory circuit for definition of waiting times 有权
标题翻译：用于定义等待时间的存储器电路中的器件
公开(公告)号：US07355921B2
公开(公告)日：2008-04-08
申请号：US11386043
申请日：2006-03-21
申请人： Andre Schaefer , Thomas Hein , Christian Weis
发明人： Andre Schaefer , Thomas Hein , Christian Weis
IPC分类号： G11C8/00
CPC分类号： G11C7/222 , G11C7/22 , G11C11/4076
摘要： A device for definition of the waiting time which should pass in a clock-controlled memory circuit after the start of a specific operation until a subsequent operation may be started. The device includes a digital timer which is arranged in the memory circuit, is switched on when the specific operation is initiated and allows the subsequent operation to be started after a defined time period has elapsed. The digital timer, after it is switched on, counts periodic counting pulses which are derived from the clock signal, in order to signal the end of the waiting time as soon as it has counted a desired number of these pulses. A waiting time adjustment apparatus is provided and is accessible via external connections of the memory circuit in order to set the desired number of counting pulses.
摘要翻译：用于定义在特定操作开始之后通过时钟控制的存储器电路的等待时间的装置，直到可以开始后续操作。该设备包括布置在存储器电路中的数字定时器，当特定操作开始时被接通，并且允许在经过限定的时间段之后开始后续操作。数字定时器在其接通之后，计数从时钟信号导出的周期性计数脉冲，以便一旦计数了所需数量的这些脉冲，就发出等待时间结束的信号。提供等待时间调整装置，并且可以通过存储器电路的外部连接来访问，以便设置所需数量的计数脉冲。

6. 发明申请

US20060233005A1 Device in a memory circuit for definition of waiting times 有权
标题翻译：用于定义等待时间的存储器电路中的器件
公开(公告)号：US20060233005A1
公开(公告)日：2006-10-19
申请号：US11386043
申请日：2006-03-21
申请人： Andre Schaefer , Thomas Hein , Christian Weis
发明人： Andre Schaefer , Thomas Hein , Christian Weis
IPC分类号： G11C19/08
CPC分类号： G11C7/222 , G11C7/22 , G11C11/4076
摘要： The invention relates to a device for definition of the waiting time which should pass in a clock-controlled memory circuit after the start of a specific operation until a subsequent operation may be started. The device includes a digital timer which is arranged in the memory circuit, is switched on when the specific operation is initiated and allows the subsequent operation to be started after a defined time period has elapsed. The digital timer, after it is switched on, counts periodic counting pulses which are derived from the clock signal, in order to signal the end of the waiting time as soon as it has counted a desired number of these pulses. A waiting time adjustment apparatus is provided and is accessible via external connections of the memory circuit in order to set the desired number of counting pulses.
摘要翻译：本发明涉及一种用于定义等待时间的装置，该等待时间应在特定操作开始之后通过时钟控制的存储器电路，直到可以开始后续操作。该设备包括布置在存储器电路中的数字定时器，当特定操作开始时被接通，并且允许在经过限定的时间段之后开始后续操作。数字定时器在其接通之后，计数从时钟信号导出的周期性计数脉冲，以便一旦计数了所需数量的这些脉冲，就发出等待时间结束的信号。提供等待时间调整装置，并且可以通过存储器电路的外部连接来访问，以便设置所需数量的计数脉冲。

7. 发明授权

US09311983B2 Dynamically applying refresh overcharge voltage to extend refresh cycle time 有权
标题翻译：动态地施加刷新过充电电压以延长刷新周期时间
公开(公告)号：US09311983B2
公开(公告)日：2016-04-12
申请号：US14320249
申请日：2014-06-30
申请人： Andre Schaefer
发明人： Andre Schaefer
IPC分类号： G11C7/00 , G11C11/406 , G11C11/4076
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40622 , G11C11/4076 , G11C11/4091 , G11C2211/4065 , G11C2211/4067 , G11C2211/4068
摘要： A refresh voltage control engine selectively applies different high voltages to use in refresh operations. The control engine can detect that a portion of a memory device needs to be refreshed, and determine that the refresh cycle time is too short for a state of the portion of the memory device. The memory device typically has an associated refresh cycle time or time between refreshes based on the device and system architecture. The control engine can generate one or more control signals to cause the system to apply an overcharge refresh to overcharge the portion of the memory device with a refresh operation to extend the refresh cycle time for the portion of the memory device.
摘要翻译：刷新电压控制引擎选择性地施加不同的高电压以用于刷新操作。控制引擎可以检测存储器件的一部分需要刷新，并且确定刷新周期时间对于存储器件的该部分的状态来说太短。存储器件通常具有基于设备和系统架构的刷新之间的相关联的刷新周期时间或时间。控制引擎可以产生一个或多个控制信号，以使系统施加过充电刷新，以使刷新操作对存储器件的一部分进行过充电，以延长存储器件部分的刷新周期时间。

8. 发明申请

US20130246734A1 Adaptive Address Mapping with Dynamic Runtime Memory Mapping Selection 有权
标题翻译：自适应地址映射与动态运行时内存映射选择
公开(公告)号：US20130246734A1
公开(公告)日：2013-09-19
申请号：US13419172
申请日：2012-03-13
申请人： Andre Schaefer , Matthias Gries
发明人： Andre Schaefer , Matthias Gries
IPC分类号： G06F12/00
CPC分类号： G06F12/063 , G06F11/3409 , G06F12/0292 , G06F12/0646 , G06F12/10 , Y02D10/13 , Y02D10/34
摘要： A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.
摘要翻译：系统监视并动态地改变计算系统运行时的内存映射。计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。

9. 发明授权

US08037375B2 Fast data eye retraining for a memory 有权
标题翻译：快速数据眼睛重新训练记忆
公开(公告)号：US08037375B2
公开(公告)日：2011-10-11
申请号：US12459420
申请日：2009-06-30
申请人： Andre Schaefer
发明人： Andre Schaefer
IPC分类号： G06F11/00
CPC分类号： G06F13/1689 , G11C5/04 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C29/02 , G11C29/023 , G11C29/50 , G11C29/50012 , G11C2029/0409 , G11C2207/2254 , Y02D10/14
摘要： A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.
摘要翻译：公开了一种方法，装置和系统。在一个实施例中，方法包括确定存储器的有效数据眼睛的左边缘和右边缘。该方法通过在存储器的操作期间周期性地检查左右边缘以进行移动来继续。如果检测到移动，则该方法使用更新的左边缘和右边缘重新训练有效的数据眼睛。

10. 发明授权

US06625065B2 Method for masking DQ bits 有权
公开(公告)号：US06625065B2
公开(公告)日：2003-09-23
申请号：US09978399
申请日：2001-10-16
申请人： Martin Gall , Andre Schaefer
发明人： Martin Gall , Andre Schaefer
IPC分类号： G11C700
CPC分类号： G11C11/4096 , G11C7/1006 , G11C7/1078
摘要： A method for masking DQ bits that are input into a semiconductor memory by a memory controller is described. In this case, the bits to be masked are provided with an increased level and therefore cannot be read into the semiconductor memory due to the increased voltage level which functions as a deactivating voltage level.

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