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1. 发明授权

US07411862B2 Control signal training 有权
标题翻译：控制信号训练
公开(公告)号：US07411862B2
公开(公告)日：2008-08-12
申请号：US11560293
申请日：2006-11-15
申请人： Thomas Hein , Aaron John Nygren , Rex Kho
发明人： Thomas Hein , Aaron John Nygren , Rex Kho
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C7/22 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A control signal training system in an integrated circuit comprises a signal transmitting unit, the signal transmitting unit outputting control signals and sampling clock signals, the control signals and the sampling clock signals having a predetermined time phase with respect to each other, a signal receiving unit, the signal receiving unit latching control signals in relation to the sampling clock signals, and an evaluation unit connected to a reading unit and the signal transmitting unit, the evaluation unit determining concordance of the control signals outputted by the signal transmitting unit and the control signals read out by the reading unit from the signal receiving unit, the evaluation unit adapting the time phase between the control signals and the sampling clock signals step-by-step until concordance of the control signals outputted by the signal transmitting unit and the control signals read out the reading unit from the signal receiving unit is determined by the evaluation unit.
摘要翻译：集成电路中的控制信号训练系统包括信号发送单元，信号发送单元输出控制信号和采样时钟信号，控制信号和采样时钟信号相对于彼此具有预定的时间相位;信号接收单元信号接收单元相对于采样时钟信号锁存控制信号，以及连接到读取单元和信号发送单元的评估单元，评估单元确定由信号发送单元输出的控制信号和控制信号的一致性由读取单元从信号接收单元读出，评估单元逐步调整控制信号与采样时钟信号之间的时间相位，直到由信号发送单元输出的控制信号和读取的控制信号的一致从信号接收单元输出读取单元由评估确定单位。

2. 发明授权

US07587571B2 Evaluation unit in an integrated circuit 有权
标题翻译：集成电路中的评估单元
公开(公告)号：US07587571B2
公开(公告)日：2009-09-08
申请号：US11564764
申请日：2006-11-29
申请人： Thomas Hein , Aaron John Nygren , Rex Kho
发明人： Thomas Hein , Aaron John Nygren , Rex Kho
IPC分类号： G06F12/00 , G06F13/00 , G06F13/42
CPC分类号： G11C5/04
摘要： An integrated circuit comprising a first terminal for exchanging signals; an evaluation unit coupled to the first terminal, the evaluation unit evaluating a signal level applied to the first terminal to determine whether or not the signal level corresponds to a predetermined signal level; and a switching unit coupled to the first terminal and to the evaluation unit, the switching unit admitting signal exchange via the first terminal if the evaluation unit does not determine the predetermined signal level, the switching unit cutting off signal exchange via the first terminal if the evaluation unit determines the predetermined signal level.
摘要翻译：一种集成电路，包括用于交换信号的第一端子; 评估单元，耦合到所述第一终端，所述评估单元评估施加到所述第一终端的信号电平，以确定所述信号电平是否对应于预定信号电平; 以及耦合到所述第一终端和所述评估单元的切换单元，所述切换单元在所述评估单元未确定所述预定信号电平时通过所述第一终端接纳信号交换，所述切换单元通过所述第一终端切断信号交换，如果评估单元确定预定信号电平。

3. 发明申请

US20080112255A1 TRAINING OF SIGNAL TRANSFER CHANNELS BETWEEN MEMORY CONTROLLER AND MEMORY DEVICE 审中-公开
标题翻译：记忆控制器与存储器件之间信号传输通道的训练
公开(公告)号：US20080112255A1
公开(公告)日：2008-05-15
申请号：US11560302
申请日：2006-11-15
申请人： Aaron John Nygren , Thomas Hein , Rex Kho
发明人： Aaron John Nygren , Thomas Hein , Rex Kho
IPC分类号： G11C8/00
CPC分类号： G11C29/02 , G11C5/04 , G11C29/025 , G11C29/50012
摘要： Apparatus and method of training a data transfer channel between a memory controller and a memory device connected to each other via a data signal transfer channel and an address signal transfer channel. The method comprises reading test data from a latching circuit connected to both an address signal input and a data or control signal output of the memory device or from a read only memory in the memory device, transferring a read signal representing the test data via the data signal transfer channel, detecting data from the read signal with a delay relative to a read clock signal; repeating the transferring, detecting steps, each time detecting the data at a different value of the delay; selecting a value of the delay, preferably a value at which the detected data equal the test data; and setting the delay to the selected value.
摘要翻译：通过数据信号传送通道和地址信号传送通道在存储器控制器和连接到彼此的存储器件之间训练数据传送通道的装置和方法。该方法包括从连接到存储器件的地址信号输入和数据或控制信号输出的存储电路或从存储器件中的只读存储器读取测试数据，经由数据传送表示测试数据的读取信号信号传输通道，相对于读取时钟信号以相对于读取时钟信号的延迟来检测来自读取信号的数据; 每次以不同的延迟值检测数据，重复传送，检测步骤; 选择延迟的值，优选地是检测数据等于测试数据的值; 并将延迟设置为所选值。

4. 发明申请

US20080115030A1 Information transmission and reception 有权
标题翻译：信息发送和接收
公开(公告)号：US20080115030A1
公开(公告)日：2008-05-15
申请号：US11599992
申请日：2006-11-15
申请人： Thomas Hein , Rex Kho , Aaron John Nygren
发明人： Thomas Hein , Rex Kho , Aaron John Nygren
IPC分类号： H03M13/03
CPC分类号： H03M5/145
摘要： An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information. Accordingly, an information receiving apparatus comprises an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.
摘要翻译：描述信息发送装置。接口包括用于有效数据字的第一输入，用于要发送的信息的第二输入和输出，其中接口提供数据字或在输出端可被识别为无效数据字的数据字，这取决于信息。因此，信息接收装置包括包括用于数据字的输入和用于信息的输出的接口，其中接口根据数据字是有效数据字还是无效数据字导出信息。

5. 发明申请

US20070283297A1 Signal processing circuit 审中-公开
标题翻译：信号处理电路
公开(公告)号：US20070283297A1
公开(公告)日：2007-12-06
申请号：US11443491
申请日：2006-05-30
申请人： Thomas Hein , Rex Kho
发明人： Thomas Hein , Rex Kho
IPC分类号： G06F17/50
CPC分类号： G11C7/22 , G11C7/222 , H04L7/02 , H04L7/0331
摘要： A signal processing circuit includes a first circuit including a first clock signal generator with an output for a first clock signal and a second clock signal generator with an output for a second clock signal and an input for a comparison signal. The second clock signal is generated by the second clock signal generator based on the comparison signal. A second circuit includes a phase detector with a first input for the first clock signal, with a second input for the second clock signal and an output for the comparison signal indicating a relation between the phases of the first clock signal received at the first input and the second clock signal received at the second input.
摘要翻译：信号处理电路包括：第一电路，包括具有用于第一时钟信号的输出的第一时钟信号发生器和具有用于第二时钟信号的输出和用于比较信号的输入的第二时钟信号发生器。第二时钟信号由第二时钟信号发生器基于比较信号产生。第二电路包括具有用于第一时钟信号的第一输入的相位检测器，具有用于第二时钟信号的第二输入和用于比较信号的输出，该输出指示在第一输入处接收到的第一时钟信号的相位之间的关系;以及在第二输入处接收的第二时钟信号。

6. 发明授权

US08201071B2 Information transmission and reception 有权
标题翻译：信息发送和接收
公开(公告)号：US08201071B2
公开(公告)日：2012-06-12
申请号：US11599992
申请日：2006-11-15
申请人： Thomas Hein , Rex Kho , Aaron John Nygren
发明人： Thomas Hein , Rex Kho , Aaron John Nygren
IPC分类号： H03M7/14
CPC分类号： H03M5/145
摘要： An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information. Accordingly, an information receiving apparatus comprises an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.
摘要翻译：描述信息发送装置。接口包括用于有效数据字的第一输入，用于要发送的信息的第二输入和输出，其中接口提供数据字或在输出端可识别为无效数据字的数据字，这取决于信息。因此，信息接收装置包括包括用于数据字的输入和用于信息的输出的接口，其中接口根据数据字是有效数据字还是无效数据字导出信息。

7. 发明申请

US20080123438A1 EVALUATION UNIT IN AN INTEGRATED CIRCUIT 有权
标题翻译：综合电路评估单位
公开(公告)号：US20080123438A1
公开(公告)日：2008-05-29
申请号：US11564764
申请日：2006-11-29
申请人： Thomas Hein , Aaron John Nygren , Rex Kho
发明人： Thomas Hein , Aaron John Nygren , Rex Kho
IPC分类号： G11C7/10
CPC分类号： G11C5/04
摘要： An integrated circuit comprising a first terminal for exchanging signals; an evaluation unit coupled to the first terminal, the evaluation unit evaluating a signal level applied to the first terminal to determine whether or not the signal level corresponds to a predetermined signal level; and a switching unit coupled to the first terminal and to the evaluation unit, the switching unit admitting signal exchange via the first terminal if the evaluation unit does not determine the predetermined signal level, the switching unit cutting off signal exchange via the first terminal if the evaluation unit determines the predetermined signal level.
摘要翻译：一种集成电路，包括用于交换信号的第一端子; 评估单元，耦合到所述第一终端，所述评估单元评估施加到所述第一终端的信号电平，以确定所述信号电平是否对应于预定信号电平; 以及耦合到所述第一终端和所述评估单元的切换单元，所述切换单元在所述评估单元未确定所述预定信号电平时通过所述第一终端接纳信号交换，所述切换单元通过所述第一终端切断信号交换，如果评估单元确定预定信号电平。

8. 发明申请

US20080112235A1 CONTROL SIGNAL TRAINING 有权
标题翻译：控制信号训练
公开(公告)号：US20080112235A1
公开(公告)日：2008-05-15
申请号：US11560293
申请日：2006-11-15
申请人： Thomas Hein , Aaron John Nygren , Rex Kho
发明人： Thomas Hein , Aaron John Nygren , Rex Kho
IPC分类号： G11C7/00
CPC分类号： G11C5/04 , G11C7/22 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A control signal training system in an integrated circuit comprises a signal transmitting unit, the signal transmitting unit outputting control signals and sampling clock signals, the control signals and the sampling clock signals having a predetermined time phase with respect to each other, a signal receiving unit, the signal receiving unit latching control signals in relation to the sampling clock signals, and an evaluation unit connected to a reading unit and the signal transmitting unit, the evaluation unit determining concordance of the control signals outputted by the signal transmitting unit and the control signals read out by the reading unit from the signal receiving unit, the evaluation unit adapting the time phase between the control signals and the sampling clock signals step-by-step until concordance of the control signals outputted by the signal transmitting unit and the control signals read out the reading unit from the signal receiving unit is determined by the evaluation unit.
摘要翻译：集成电路中的控制信号训练系统包括信号发送单元，信号发送单元输出控制信号和采样时钟信号，控制信号和采样时钟信号相对于彼此具有预定的时间相位;信号接收单元信号接收单元相对于采样时钟信号锁存控制信号，以及连接到读取单元和信号发送单元的评估单元，评估单元确定由信号发送单元输出的控制信号和控制信号的一致性由读取单元从信号接收单元读出，评估单元逐步调整控制信号与采样时钟信号之间的时间相位，直到由信号发送单元输出的控制信号和读取的控制信号的一致从信号接收单元输出读取单元由评估确定单位。

9. 发明申请

US20080114947A1 WRITE ACCESS AND SUBSEQUENT READ ACCESS TO A MEMORY DEVICE 有权
标题翻译：写访问和后续读取访问存储器件
公开(公告)号：US20080114947A1
公开(公告)日：2008-05-15
申请号：US11936663
申请日：2007-11-07
申请人： Martin Brox , Rex Kho
发明人： Martin Brox , Rex Kho
IPC分类号： G06F12/00
CPC分类号： G11C7/10 , G06F13/1673 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1093
摘要： A memory device has a first memory area and a second memory area. A method for operating the memory device includes a write access to the first memory area and a read access to the second memory area.
摘要翻译：存储器设备具有第一存储器区域和第二存储器区域。用于操作存储器件的方法包括对第一存储器区域的写访问和对第二存储器区域的读访问。

10. 发明申请

US20070245096A1 Finding a data pattern in a memory 有权
标题翻译：在内存中查找数据模式
公开(公告)号：US20070245096A1
公开(公告)日：2007-10-18
申请号：US11386176
申请日：2006-03-22
申请人： Stefan Dietrich , Rex Kho
发明人： Stefan Dietrich , Rex Kho
IPC分类号： G06F13/00
CPC分类号： G06F13/1689 , G11C7/1006 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C15/04
摘要： A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a multiplexer. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for shifting the FIFO output pointer based on data read from the FIFO cells. The multiplexer is for receiving the value of the FIFO output pointer from the output pointer counter. The multiplexer is also for receiving the multiplexing information for shifting the FIFO output pointer. The multiplexer is further for shifting the value of the FIFO output pointer based on the multiplexing information.
摘要翻译：存储器包括多个先进先出（FIFO）单元，输出指针计数器，写入训练块和多路复用器。输出指针计数器用于切换FIFO单元格中FIFO输出指针的值。写入训练块用于根据从FIFO单元读取的数据产生用于移位FIFO输出指针的信息。多路复用器用于从输出指针计数器接收FIFO输出指针的值。复用器还用于接收用于移位FIFO输出指针的复用信息。复用器还用于基于复用信息来移位FIFO输出指针的值。

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