专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07517796B2 Method for patterning submicron pillars 有权
标题翻译：图案亚微米柱的方法
公开(公告)号：US07517796B2
公开(公告)日：2009-04-14
申请号：US11061952
申请日：2005-02-17
申请人： Usha Raghuram , Michael W. Konevecki
发明人： Usha Raghuram , Michael W. Konevecki
IPC分类号： H01L21/44
CPC分类号： H01L29/868 , H01L21/0337 , H01L21/3086 , H01L27/1021 , H01L29/456 , H01L29/66136 , H01L29/8615 , Y10S438/947
摘要： The present invention provides for a method to pattern and etch very small dimension pillars, for example in a memory array. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using methods according to the present invention, these photoresist pillars are printed and developed larger than their intended final dimension, such that they have increased mechanical strength, then are shrunk to the desired dimension during a preliminary etch performed before the etch of underlying material begins.
摘要翻译：本发明提供了一种用于对例如在存储器阵列中的非常小的尺寸柱进行图案化和蚀刻的方法。当柱的尺寸变得非常小时，用于图案化的光致抗蚀剂柱可能不具有足够的机械强度以在光刻胶曝光和显影过程中存活。使用根据本发明的方法，这些光致抗蚀剂柱被印刷和显影成大于其预期的最终尺寸，使得它们具有增加的机械强度，然后在下层材料的蚀刻开始之前进行的初步蚀刻期间收缩到期望的尺寸。

42. 发明申请

US20090087979A1 DUAL DAMASCENE WITH AMORPHOUS CARBON FOR 3D DEEP VIA/TRENCH APPLICATION 有权
标题翻译：具有用于3D深度穿透/拉伸应用的非晶碳的双重损伤
公开(公告)号：US20090087979A1
公开(公告)日：2009-04-02
申请号：US11864759
申请日：2007-09-28
申请人： Usha Raghuram , Michael W. Konevecki
发明人： Usha Raghuram , Michael W. Konevecki
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L27/101 , H01L27/1021
摘要： A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit line for memory cells, or to provide other routing paths. A dual damascene process can be used in which the via is formed first and the trench is formed second, or the trench is formed first and the via is formed second. The technique is particularly suitable for deep via applications, such as for via depths of greater than 1 μm. A dielectric antireflective coating, optionally with a bottom antireflective coating, can be used to etch an amorphous carbon layer to provide the amorphous carbon hard mask.
摘要翻译：一种用于制造使用无定形碳硬掩模蚀刻通孔和沟槽的3-D单片存储器件的方法。该通孔作为多级垂直互连在设备的多个级别中延伸。沟槽横向延伸，例如为存储器单元提供字线或位线，或提供其它布线路径。可以使用双镶嵌工艺，其中通孔首先形成，并且沟槽形成第二，或者沟槽首先形成，并且通孔形成第二。该技术特别适用于深通孔应用，例如通过大于1um的深度。可以使用任选具有底部抗反射涂层的电介质抗反射涂层来蚀刻无定形碳层以提供无定形碳硬掩模。

43. 发明申请

US20080116441A1 NONVOLATILE PHASE CHANGE MEMORY CELL HAVING A REDUCED CONTACT AREA 有权
标题翻译：非易失性相变存储器单元，具有减少的接触面积
公开(公告)号：US20080116441A1
公开(公告)日：2008-05-22
申请号：US11560791
申请日：2006-11-16
申请人： Usha Raghuram , S. Brad Herner
发明人： Usha Raghuram , S. Brad Herner
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： A nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits is described. To form this cell, a conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.
摘要翻译：描述了在诸如硫族化物的相变材料和小于光刻极限的热源之间具有接触面积的非易失性存储单元。为了形成该电池，导电或半导体柱在电介质表面露出并通过选择性蚀刻凹陷。间隔材料的薄的共形层被沉积在电介质顶表面，柱顶表面和凹槽的侧壁上，然后通过无功蚀刻从水平表面去除，在侧壁上留下间隔，限定内部减小的体积休息。相变材料沉积在间隔物内，具有减小的与下面的导电或半导体柱的接触面积。

44. 发明授权

US06406640B1 Plasma etching method 失效
标题翻译：等离子蚀刻法
公开(公告)号：US06406640B1
公开(公告)日：2002-06-18
申请号：US09546714
申请日：2000-04-10
申请人： Chan-lon Yang , Usha Raghuram , Kimberley A. Kaufman , Daniel Arnzen , James Nulty
发明人： Chan-lon Yang , Usha Raghuram , Kimberley A. Kaufman , Daniel Arnzen , James Nulty
IPC分类号： H01L2100
CPC分类号： H01L21/31116
摘要： The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus in which a concentration of oxygen at flash striking is greater than a concentration during etching.
摘要翻译：本发明涉及一种等离子体蚀刻方法和操作等离子体蚀刻装置的方法，其中闪光时的氧浓度大于蚀刻期间的浓度。

45. 发明授权

US6165375A Plasma etching method 失效
标题翻译：等离子蚀刻法
公开(公告)号：US6165375A
公开(公告)日：2000-12-26
申请号：US935705
申请日：1997-09-23
申请人： Chan-lon Yang , Usha Raghuram , Kimberley A. Kaufman , Daniel Arnzen , James Nulty
发明人： Chan-lon Yang , Usha Raghuram , Kimberley A. Kaufman , Daniel Arnzen , James Nulty
IPC分类号： H01L21/311 , B44C1/22
CPC分类号： H01L21/31116
摘要： The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus.
摘要翻译：等离子体蚀刻方法技术领域本发明涉及等离子体蚀刻方法和等离子体蚀刻装置的操作方法。

46. 发明授权

US08987119B2 Pillar devices and methods of making thereof 有权
公开(公告)号：US08987119B2
公开(公告)日：2015-03-24
申请号：US13026381
申请日：2011-02-14
申请人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
发明人： Vance Dunton , S. Brad Herner , Paul Wai Kie Poon , Chuanbin Pan , Michael Chan , Michael Konevecki , Usha Raghuram
IPC分类号： H01L21/36 , H01L27/102 , H01L29/861 , H01L29/868
CPC分类号： H01L27/1021 , H01L29/8613 , H01L29/8615 , H01L29/868
摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.

47. 发明授权

US08759176B2 Patterning of submicron pillars in a memory array 有权
标题翻译：存储器阵列中亚微米柱的图案化
公开(公告)号：US08759176B2
公开(公告)日：2014-06-24
申请号：US12422072
申请日：2009-04-10
申请人： Usha Raghuram , Michael W. Konevecki
发明人： Usha Raghuram , Michael W. Konevecki
IPC分类号： H01L21/8234
CPC分类号： H01L29/868 , H01L21/0337 , H01L21/3086 , H01L27/1021 , H01L29/456 , H01L29/66136 , H01L29/8615 , Y10S438/947
摘要： Methods in accordance with the invention involve patterning and etching very small dimension pillars, such as in formation of a memory array in accordance with the invention. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using methods according to the present invention, these photoresist pillars are printed and developed larger than their intended final dimension, such that they have increased mechanical strength, then are shrunk to the desired dimension during a preliminary etch performed before the etch of underlying material begins.
摘要翻译：根据本发明的方法包括图案化和蚀刻非常小尺寸的柱，例如根据本发明形成存储器阵列。当柱的尺寸变得非常小时，用于图案化的光致抗蚀剂柱可能不具有足够的机械强度以在光刻胶曝光和显影过程中存活。使用根据本发明的方法，这些光致抗蚀剂柱被印刷和显影成大于其预期的最终尺寸，使得它们具有增加的机械强度，然后在下层材料的蚀刻开始之前进行的初步蚀刻期间收缩到期望的尺寸。

48. 发明申请

US20140055152A1 CIRCULAR TRANSMISSION LINE METHODS COMPATIBLE WITH COMBINATORIAL PROCESSING OF SEMICONDUCTORS 有权
标题翻译：圆形传输线方法与半导体的组合处理兼容
公开(公告)号：US20140055152A1
公开(公告)日：2014-02-27
申请号：US13594292
申请日：2012-08-24
申请人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
发明人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
IPC分类号： G01R27/08
CPC分类号： G01R27/08 , G01R31/2831 , H01L22/14 , H01L22/20
摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要翻译：描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

49. 发明申请

US20120200852A1 SPECTROSCOPY AND SPECTRAL IMAGING METHODS AND APPARATUS 审中-公开
标题翻译：光谱和光谱成像方法和装置
公开(公告)号：US20120200852A1
公开(公告)日：2012-08-09
申请号：US13229185
申请日：2011-09-09
申请人： Francisco Tejada , Peter Griffin , Ricky James Morgan , Ali Abtahi , Usha Raghuram , Frida Stromqvist Vetelino , Roderick Pearson
发明人： Francisco Tejada , Peter Griffin , Ricky James Morgan , Ali Abtahi , Usha Raghuram , Frida Stromqvist Vetelino , Roderick Pearson
IPC分类号： G01J3/28 , H01B13/00 , B32B38/00 , B32B37/00 , B44C1/22
CPC分类号： H01L27/14629 , G01J3/12 , G01J3/26
摘要： The invention pertains to a new type of spectroscope comprising an array of Fabry-Perot cells having no moving parts and that can be fabricated inexpensively using semiconductor fabrication techniques.
摘要翻译：本发明涉及一种新型的分光镜，其包括不具有运动部分并且可以使用半导体制造技术廉价制造的法布里 - 珀罗细胞阵列。

50. 发明授权

US08084366B2 Modified DARC stack for resist patterning 有权
标题翻译：用于抗蚀剂图案化的改进的DARC叠层
公开(公告)号：US08084366B2
公开(公告)日：2011-12-27
申请号：US12213273
申请日：2008-06-17
申请人： Michael Chan , Usha Raghuram
发明人： Michael Chan , Usha Raghuram
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0332 , H01L21/0276 , H01L21/3081 , H01L21/31144 , H01L21/32139 , H01L27/101
摘要： A method of making a device includes forming a device layer, forming an organic hard mask layer over the device layer, forming a first oxide hard mask layer over the organic hard mask layer, forming a DARC layer over the first oxide hard mask layer, forming a photoresist layer over the DARC layer, patterning the photoresist layer to form a photoresist pattern, and transferring the photoresist pattern to the device layer using the DARC layer, the first oxide hard mask layer and the organic hard mask layer.
摘要翻译：制造器件的方法包括形成器件层，在器件层上形成有机硬掩模层，在有机硬掩模层上形成第一氧化物硬掩模层，在第一氧化物硬掩模层上形成DARC层，形成在DARC层上的光致抗蚀剂层，图案化光致抗蚀剂层以形成光致抗蚀剂图案，并且使用DARC层，第一氧化物硬掩模层和有机硬掩模层将光致抗蚀剂图案转移到器件层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式