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1. 发明申请

US20130168231A1 Method For Sputter Deposition And RF Plasma Sputter Etch Combinatorial Processing 审中-公开
标题翻译：溅射沉积和RF等离子体溅射蚀刻组合处理方法
公开(公告)号：US20130168231A1
公开(公告)日：2013-07-04
申请号：US13341993
申请日：2011-12-31
申请人： Hong Sheng Yang , Kent Riley Child , Brian Hatcher , ShouQian Shao , Jingang Su , James Tsung
发明人： Hong Sheng Yang , Kent Riley Child , Brian Hatcher , ShouQian Shao , Jingang Su , James Tsung
IPC分类号： C23C14/34 , C23F1/00
CPC分类号： H01J37/34 , C23C14/042 , C23C14/345 , C23C14/351 , C23C14/352 , H01J37/32091 , H01J37/32651
摘要： Combinatorial processing of a substrate comprising site-isolated sputter deposition and site-isolated plasma etching can be performed in a same process chamber. The process chamber, configured to carry out sputter deposition and RF plasma etch, comprises a grounded shield having at least an aperture disposed above the substrate to form a small, dark space gap to reduce or eliminate any plasma formation within the gap
摘要翻译：包括现场分离的溅射沉积和位置分离的等离子体蚀刻的基板的组合处理可以在相同的处理室中进行。构造成执行溅射沉积和RF等离子体蚀刻的处理室包括接地屏蔽，其具有设置在衬底上方的至少一个孔，以形成小的，较暗的空间间隙，以减少或消除间隙内的任何等离子体形成

2. 发明授权

US08854067B2 Circular transmission line methods compatible with combinatorial processing of semiconductors 有权
标题翻译：圆形传输线方法兼容半导体的组合处理
公开(公告)号：US08854067B2
公开(公告)日：2014-10-07
申请号：US13594292
申请日：2012-08-24
申请人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
发明人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
IPC分类号： G01R27/08 , G01R31/28
CPC分类号： G01R27/08 , G01R31/2831 , H01L22/14 , H01L22/20
摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要翻译：描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

3. 发明授权

US6149784A Sputtering chamber shield promoting reliable plasma ignition 失效
标题翻译：溅射室屏蔽促进可靠的等离子体点火
公开(公告)号：US6149784A
公开(公告)日：2000-11-21
申请号：US425583
申请日：1999-10-22
申请人： Jingang Su , Nelson A. Yee , John C. Forster , Kenny King-Tai Ngan , Lisa L. Yang
发明人： Jingang Su , Nelson A. Yee , John C. Forster , Kenny King-Tai Ngan , Lisa L. Yang
IPC分类号： H01L21/205 , C23C14/34 , C23C14/35 , C23C14/56 , H01J37/34 , H01L21/28 , H01L21/285
CPC分类号： H01J37/3441 , C23C14/3407 , C23C14/35 , C23C14/564 , H01J37/3402
摘要： A shield for a DC magnetron sputtering reactor, particularly advantageous for reliably igniting the plasma used in sputtering a ferromagnetic material such as cobalt or nickel. The grounded shield includes a slanted portion separated from the beveled periphery of the target by a small gap operating as a dark space. The shield also includes a straight cylindrical portion surrounding the main processing area. The slanted portion is joined to the cylindrical portion at a knee According to one embodiment of the invention, the knee is located greater than 9 mm from the face of the target and at a radial position at least 1 mm inward of the outer periphery of the target face.
摘要翻译：用于DC磁控溅射反应器的屏蔽，特别有利于可靠地点燃用于溅射铁磁材料如钴或镍的等离子体。接地的屏蔽件包括一个与目标的斜面周边分开的倾斜部分，作为暗空间工作的小间隙。屏蔽还包括围绕主处理区域的直圆柱形部分。倾斜部分在膝盖处连接到圆柱形部分根据本发明的一个实施例，膝盖位于距目标的表面大于9mm处，并且位于距离靶的外周至少1mm内侧的径向位置处目标面。

4. 发明授权

US06313042B1 Cleaning contact with successive fluorine and hydrogen plasmas 失效
标题翻译：与连续的氟和氢等离子体清洁接触
公开(公告)号：US06313042B1
公开(公告)日：2001-11-06
申请号：US09390135
申请日：1999-09-03
申请人： Barney M. Cohen , Jingang Su , Kenny King-Tai Ngan , Jr-Jyan Chen
发明人： Barney M. Cohen , Jingang Su , Kenny King-Tai Ngan , Jr-Jyan Chen
IPC分类号： H01L21302
CPC分类号： H01L21/02063 , H01L21/76814 , H01L21/76843 , H01L21/76844 , Y10S438/906
摘要： A method of cleaning a contact area of a semiconductor or metal region on a substrate of an electronic device. First, the contact area is cleaned by exposing the substrate to a plasma that includes fluorine-containing species. Second, the substrate is exposed to a second atmosphere that scavenges fluorine, preferably formed by plasma decomposition of a hydrogen-containing gas. The second atmosphere removes any fluorine residue remaining on the contact area and overcomes any need to include argon sputtering in the cleaning process. Another aspect of the invention is a method of depositing a refractory metal over a contact area of a semiconductor region on a substrate. The contact area is cleaned according to the two-step process of the preceding paragraph. Then a refractory metal is deposited over the contact area. The two-step cleaning process can reduce the electrical resistance between the refractory metal and the semiconductor region. Furthermore, if the substrate is annealed to interdiffuse atoms of the semiconductor material and the refractory metal, the two-step cleaning process can reduce the anneal temperature required to achieve a desired low electrical resistance.
摘要翻译：一种清洁电子设备的基板上的半导体或金属区域的接触区域的方法。首先，通过将衬底暴露于包含含氟物质的等离子体来清洁接触区域。其次，将基板暴露于清除氟的第二气氛，优选通过含氢气体的等离子体分解形成。第二个气氛除去残留在接触区域上的任何氟残余物，并且克服了在清洗过程中包括氩气溅射的任何需要。本发明的另一方面是在基板上的半导体区域的接触区域上沉积难熔金属的方法。接触面积按前款两步法清洗。然后在接触区域上沉积难熔金属。两步清洁工艺可以降低难熔金属和半导体区域之间的电阻。此外，如果衬底对半导体材料和难熔金属的相互扩散原子退火，则两步清洁工艺可以降低实现期望的低电阻所需的退火温度。

5. 发明授权

US06383915B1 Tailoring of a wetting/barrier layer to reduce electromigration in an aluminum interconnect 失效
标题翻译：调整润湿/阻隔层以减少铝互连中的电迁移
公开(公告)号：US06383915B1
公开(公告)日：2002-05-07
申请号：US09244280
申请日：1999-02-03
申请人： Jingang Su , Gongda Yao , Zhang Xu , Fusen Chen
发明人： Jingang Su , Gongda Yao , Zhang Xu , Fusen Chen
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76876 , H01L21/76877
摘要： We have discovered particular wetting layer or wetting/barrier layer structures which enable depositing of overlying aluminum interconnect layers having texturing sufficient to provide a Rocking Curve FWHM angle &thgr; of about 1° or less. The aluminum interconnect layer exhibiting a Rocking Curve FWHM angle &thgr; of about 1° or less exhibits excellent electromigration properties. In addition when the aluminum layer is subsequently pattern etched, the sidewalls of the etched aluminum pattern exhibit a surprising reduction in pitting compared with pattern etched aluminum layers exhibiting higher Rocking Curve FWHM angles.
摘要翻译：我们已经发现了特定的润湿层或润湿/阻挡层结构，其能够沉积具有足以提供约1°或更小的摇摆曲线FWHM角度θ的<111>纹理的上覆铝互连层。表现出约1°或更小的摇摆曲线FWHM角度θ的铝互连层表现出优异的电迁移性能。此外，当铝层随后进行图案蚀刻时，与显示较高的摇摆曲线FWHM角度的图案蚀刻的铝层相比，蚀刻的铝图案的侧壁显示出令人惊讶的点蚀减少。

6. 发明授权

US6110836A Reactive plasma etch cleaning of high aspect ratio openings 有权
标题翻译：反应性等离子体蚀刻清洗高纵横比开口
公开(公告)号：US6110836A
公开(公告)日：2000-08-29
申请号：US298065
申请日：1999-04-22
申请人： Barney M. Cohen , Jingang Su , Kenny King-Tai Ngan
发明人： Barney M. Cohen , Jingang Su , Kenny King-Tai Ngan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/31116 , H01L21/76804 , H01L21/76814
摘要： Native oxides can be removed from a substrate having high aspect ratio openings therein by using a plasma gas precursor mixture of a reactive halogen-containing gas and a carrier gas such as helium. The lightweight ions generated in the plasma react with oxygen to produce very volatile oxygen-containing species that can be readily removed through the exhaust system of the plasma chamber, preventing re-deposition of oxides on the surface of the substrate or on the sidewalls or bottom of the openings. When the substrate is mounted in a plasma chamber having dual power sources that can form a plasma above the substrate and can apply bias to the substrate, tapered openings are formed rapidly that can be readily filled without forming voids.
摘要翻译：可以通过使用反应性含卤素气体和诸如氦的载气的等离子体气体前体混合物，从具有高纵横比孔的基底中除去天然氧化物。在等离子体中产生的轻质离子与氧反应产生非常易挥发的含氧物质，其可以通过等离子体室的排气系统容易地除去，从而防止氧化物在基材表面或侧壁或底部再沉积的开口。当基板安装在具有双电源的等离子体室中时，其可以在基板上形成等离子体并且可以向基板施加偏压，所以快速形成锥形开口，其可容易地填充而不形成空隙。

7. 发明申请

US20140055152A1 CIRCULAR TRANSMISSION LINE METHODS COMPATIBLE WITH COMBINATORIAL PROCESSING OF SEMICONDUCTORS 有权
标题翻译：圆形传输线方法与半导体的组合处理兼容
公开(公告)号：US20140055152A1
公开(公告)日：2014-02-27
申请号：US13594292
申请日：2012-08-24
申请人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
发明人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
IPC分类号： G01R27/08
CPC分类号： G01R27/08 , G01R31/2831 , H01L22/14 , H01L22/20
摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要翻译：描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

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