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41. 发明授权

US06326321B1 Methods of forming a layer of silicon nitride in semiconductor fabrication processes 失效
标题翻译：在半导体制造工艺中形成氮化硅层的方法
公开(公告)号：US06326321B1
公开(公告)日：2001-12-04
申请号：US09604849
申请日：2000-06-27
申请人： Scott Jeffrey DeBoer , John T. Moore , Mark Fischer , Randhir P. S. Thakur
发明人： Scott Jeffrey DeBoer , John T. Moore , Mark Fischer , Randhir P. S. Thakur
IPC分类号： H01L2131
CPC分类号： H01L21/28123 , H01L21/0276 , H01L21/31144 , H01L21/3185
摘要： In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the silicon nitride layer with silicon, the portion comprising less than or equal to about 95% of the thickness of the layer of silicon nitride. In another aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) increasing a refractive index of a first portion of the thickness of the silicon nitride layer relative to a refractive index of a second portion of the silicon nitride layer, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer. In yet another aspect, the invention includes semiconductor wafer assembly, comprising: a) a semiconductor wafer substrate; and b) a layer of silicon nitride over the substrate, the layer comprising a thickness and two portions elevationally displaced relative to one another, a first of the two portions having less resistance than a second of the two portions, the first portion comprising less than or equal to about 95% of the thickness of the silicon nitride layer.
摘要翻译：一方面，本发明包括半导体制造工艺，其包括：a）提供衬底; b）在衬底上形成氮化硅层，该层具有厚度; 以及c）用硅富集氮化硅层的一部分厚度，该部分包含小于或等于氮化硅层厚度的约95％。在另一方面，本发明包括半导体制造工艺，其包括：a）提供衬底; b）在衬底上形成氮化硅层，该层具有厚度; 以及c）相对于所述氮化硅层的第二部分的折射率增加所述氮化硅层的厚度的第一部分的折射率，所述第一部分包括小于或等于所述氮化硅层的厚度的约95％氮化硅层。在另一方面，本发明包括半导体晶片组件，包括：a）半导体晶片衬底; 以及b）在所述衬底上的一层氮化硅，所述层包括相对于彼此高度位移的厚度和两个部分，所述两个部分中的第一部分具有比所述两个部分中的第二部分更小的电阻，所述第一部分包括小于或等于氮化硅层厚度的约95％。

42. 发明授权

US06323139B1 Semiconductor processing methods of forming photoresist over silicon nitride materials 失效
标题翻译：在氮化硅材料上形成光致抗蚀剂的半导体加工方法
公开(公告)号：US06323139B1
公开(公告)日：2001-11-27
申请号：US09457093
申请日：1999-12-07
申请人： John T. Moore , Scott Jeffrey DeBoer , Mark Fischer , J. Brett Rolfson , Annette L. Martin , Ardavan Niroomand
发明人： John T. Moore , Scott Jeffrey DeBoer , Mark Fischer , J. Brett Rolfson , Annette L. Martin , Ardavan Niroomand
IPC分类号： H01L2131
CPC分类号： H01L21/0217 , G03F7/091 , H01L21/022 , H01L21/02271 , H01L21/02304 , H01L21/02362 , H01L21/0274 , H01L21/0332 , H01L21/31144 , H01L21/312 , H01L21/3185
摘要： In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer. In another aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; c) forming a photoresist over and against the barrier layer; d) exposing the photoresist to a patterned beam of light to render at least one portion of the photoresist more soluble in a solvent than an other portion, the barrier layer being an antireflective surface that absorbs light passing through the photoresist; and e) exposing the photoresist to the solvent to remove the at least one portion while leaving the other portion over the barrier layer. In yet another aspect, the invention includes a semiconductor wafer assembly, comprising: a) a silicon nitride material, the material having a surface; b) a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) a photoresist over and against the barrier layer.
摘要翻译：一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上形成光致抗蚀剂。另一方面，本发明包括半导体处理方法，包括：a）提供具有表面的氮化硅材料; b）在所述材料的表面上形成阻挡层，所述阻挡层包含硅和氮; c）在阻挡层上形成光致抗蚀剂; d）将所述光致抗蚀剂暴露于图案化的光束以使所述光致抗蚀剂的至少一部分在溶剂中比其它部分更易溶，所述阻挡层是吸收通过所述光致抗蚀剂的光的抗反射表面; 以及e）将所述光致抗蚀剂暴露于所述溶剂以除去所述至少一个部分，同时将所述另一部分留在所述阻挡层上。在另一方面，本发明包括半导体晶片组件，包括：a）氮化硅材料，该材料具有表面; b）在所述材料的表面上的阻挡层，所述阻挡层包含硅和氮; 以及c）在所述阻挡层上并抵靠所述阻挡层的光致抗蚀剂。

43. 发明授权

US6096660A Method for removing undesirable second oxide while minimally affecting a desirable first oxide 失效
标题翻译：用于去除不期望的第二氧化物同时最小化影响所需的第一氧化物的方法
公开(公告)号：US6096660A
公开(公告)日：2000-08-01
申请号：US915874
申请日：1997-08-21
申请人： David L. Chapek , John T. Moore
发明人： David L. Chapek , John T. Moore
IPC分类号： H01L21/311 , H01L21/314 , H01L21/762 , H01L21/31 , H01L21/76
CPC分类号： H01L21/3144 , H01L21/31111 , H01L21/76202
摘要： The present invention relates generally to removing an undesirable second oxide, while minimally affecting a desirable first oxide, on an integrated circuit. The integrated circuit may be part of a larger system.The second oxide is first converted to another material, such as oxynitride. The other material has differing characteristics, such as etching properties, so that it can then be removed, without substantially diminishing the first oxide.The conversion may be accomplished by heating. Heating may be accomplished by rapid thermal or furnace processing. Subsequently, the other material is removed from the integrated circuit, for example by hot phosphoric etching, so that the desirable first oxide is not substantially affected.
摘要翻译：本发明一般涉及在集成电路上去除不理想的第二氧化物，同时最小程度地影响所需的第一氧化物。集成电路可能是较大系统的一部分。首先将第二氧化物转化为另一种材料，例如氧氮化物。另一种材料具有不同的特性，例如蚀刻性质，使得其可被除去，而基本上不会减少第一氧化物。转化可以通过加热来完成。加热可以通过快速热处理或炉加工来完成。随后，例如通过热磷蚀刻从集成电路中除去另一种材料，使得所需的第一氧化物基本上不受影响。

44. 发明授权

US6051480A Trench isolation for semiconductor devices 失效
标题翻译：半导体器件的沟槽隔离
公开(公告)号：US6051480A
公开(公告)日：2000-04-18
申请号：US993329
申请日：1997-12-18
申请人： John T. Moore , David L. Chapek
发明人： John T. Moore , David L. Chapek
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the non-trench area, similar amounts of material are removed in both the trench area and non-trench area in a subsequent etching process. Consequently, formation of notches and grooves in the semiconductor structure is minimized. A sacrificial oxide layer may be made by depositing a layer of a suitable material on the surface of a semiconductor structure. By depositing a sacrificial oxide layer instead of thermally growing a sacrificial oxide layer, grooves and the notches in the trench areas are filled by the deposited material.
摘要翻译：在蚀刻沟槽隔离结构中，衬垫氧化物或牺牲氧化物可以形成为与沟槽填料基本上相同（或更高）的蚀刻速率。因为沟槽区域中的蚀刻速率基本上类似于（或小于）非沟槽区域中的蚀刻速率，所以在随后的蚀刻工艺中，在沟槽区域和非沟槽区域中去除相似量的材料。因此，半导体结构中的凹口和凹槽的形成最小化。可以通过在半导体结构的表面上沉积合适的材料层来制造牺牲氧化物层。通过沉积牺牲氧化物层而不是热生长牺牲氧化物层，沟槽区域中的凹槽和凹口被沉积的材料填充。

45. 发明授权

US5985771A Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers 失效
公开(公告)号：US5985771A
公开(公告)日：1999-11-16
申请号：US57152
申请日：1998-04-07
申请人： John T. Moore , Scott J. DeBoer , Mark Fischer
发明人： John T. Moore , Scott J. DeBoer , Mark Fischer
IPC分类号： H01L21/318 , H01L21/32 , H01L21/762
CPC分类号： H01L21/3185 , H01L21/32 , H01L21/76202
摘要： In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness. In yet other aspects, the invention includes semiconductive wafer assemblies.

46. 发明授权

US4452124A Stabilizing tab for missile launcher 失效
标题翻译：导弹发射器稳定标签
公开(公告)号：US4452124A
公开(公告)日：1984-06-05
申请号：US473929
申请日：1983-03-10
申请人： Richard C. Morenus , John T. Moore
发明人： Richard C. Morenus , John T. Moore
IPC分类号： F41A27/30 , F41F3/045 , F41F3/04
CPC分类号： F41F3/045 , F41A27/30
摘要： A launch tube (2) for launching a missile (4) is supported by a single base (6) which enables the tube (2) to pivot about orthogonal yaw and pitch axes. An aerodynamic stabilizing trim tab (20) is positioned within the interior rear of the launch tube (2). During launch, exhaust gases from the missile (4) flow over the trim tab (20), producing a lift torque which balances the torque about the pitch axis caused by gravity acting upon the missile (4). This gravitational torque would otherwise tend to pull the nose of the launch tube (2) increasingly downward as the missile (4) is launched. The angle of incidence of the trim tab (20), its surface area, and its distance from the pitch axis are varied to adjust the lift torque and the drag attributable to the trim tab (20). The drag is used to balance forward frictional force upon the launch tube (2) caused by the motion of the missile (4). The pitch torques and the linear forces are balanced simultaneously.
摘要翻译：用于发射导弹（4）的发射管（2）由单个基座（6）支撑，其使得管（2）能够绕正交偏航和俯仰轴线枢转。气动稳定装饰片（20）位于发射管（2）的内部后部。在发射期间，来自导弹（4）的废气流过修剪片（20），产生提升力矩，其平衡由作用在导弹（4）上的重力引起的俯仰轴的扭矩。否则，随着导弹（4）的发射，这种引力将会倾向于使发射管（2）的鼻子越来越下降。修剪突片（20）的入射角，其表面积和与俯仰轴线的距离是变化的，以调节提升扭矩和归因于修剪突片（20）的阻力。该拖曳用于平衡由导弹（4）的运动引起的发射管（2）上的前进摩擦力。桨距扭矩和线性力同时平衡。

47. 发明申请

US20120068141A1 SILVER-SELENIDE/CHALCOGENIDE GLASS STACK FOR RESISTANCE VARIABLE MEMORY 有权
标题翻译：用于电阻可变存储器的银 - 硒化物/氯乙烯玻璃堆叠
公开(公告)号：US20120068141A1
公开(公告)日：2012-03-22
申请号：US13303276
申请日：2011-11-23
申请人： Kristy A. Campbell , John T. Moore
发明人： Kristy A. Campbell , John T. Moore
IPC分类号： H01L45/00 , H01L21/62
CPC分类号： G11C13/0011 , G11C2213/51 , G11C2213/56 , H01L45/085 , H01L45/1233 , H01L45/143 , H01L45/1616 , H01L45/1625
摘要： The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100-x composition.
摘要翻译：本发明涉及用于提供具有改进的数据保持和切换特性的电阻可变存储元件的方法和装置。根据本发明的实施例，提供了一种电阻可变存储元件，其在玻璃层之间具有至少一个硒化银层，其中至少一个玻璃层是硫族化物玻璃，优选具有GexSe100-x组成。

48. 发明授权

US07863597B2 Resistance variable memory devices with passivating material 有权
标题翻译：具有钝化材料的电阻变量存储器件
公开(公告)号：US07863597B2
公开(公告)日：2011-01-04
申请号：US12010420
申请日：2008-01-24
申请人： Kristy A. Campbell , Terry L. Gilton , John T. Moore , Jiutao Li
发明人： Kristy A. Campbell , Terry L. Gilton , John T. Moore , Jiutao Li
IPC分类号： H01L47/00
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1641 , H01L45/1658 , H01L45/1683
摘要： A method of forming a non-volatile resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide comprising material is formed over the first conductive electrode material. Such comprises the metal and AxBy, where “B” is selected from S, Se and Te and mixtures thereof, and where “A” comprises at least one element which is selected from Group 13, Group 14, Group 15, or Group 17 of the periodic table. In one aspect, the chalcogenide comprising material is exposed to and HNO3 solution. In one aspect the outer surface is oxidized effective to form a layer comprising at least one of an oxide of “A” or an oxide of “B”. In one aspect, a passivating material is formed over the metal doped chalcogenide comprising material. A second conductive electrode material is deposited, and a second conductive electrode material of the device is ultimately formed therefrom.
摘要翻译：形成非易失性电阻可变器件的方法包括在衬底上形成第一导电电极材料。在第一导电电极材料上形成包含材料的掺杂金属的硫族化物。这样包括金属和AxBy，其中“B”选自S，Se和Te及其混合物，其中“A”包含至少一种选自第13族，第14族，第15族或第17族的元素周期表。在一个方面，将包含硫属元素的材料暴露于HNO 3溶液中。在一个方面，外表面被有效地氧化以形成包含“A”的氧化物或“B”的氧化物中的至少一种的层。在一个方面，在包含金属的硫族化物的材料上形成钝化材料。沉积第二导电电极材料，并且最终由器件的第二导电电极材料形成。

49. 发明授权

US07723713B2 Layered resistance variable memory device and method of fabrication 有权
标题翻译：分层电阻可变存储器件及其制造方法
公开(公告)号：US07723713B2
公开(公告)日：2010-05-25
申请号：US11443266
申请日：2006-05-31
申请人： Kristy A. Campbell , Jiutao Li , Allen McTeer , John T. Moore
发明人： Kristy A. Campbell , Jiutao Li , Allen McTeer , John T. Moore
IPC分类号： H01L47/00
CPC分类号： G11C13/0011 , G11C2213/51 , G11C2213/56 , H01L45/085 , H01L45/1233 , H01L45/143 , H01L45/1616 , H01L45/1625
摘要： The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to one embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between two glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100-x composition. According to another embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between chalcogenide glass layers and further having a silver layer above at least one of said chalcogenide glass layers and a conductive adhesion layer above said silver layer. According to the another embodiment of the invention, a resistance variable memory element is provided having a first chalcogenide glass layer, a silver layer over said chalcogenide glass layer, a second chalcogenide glass layer over said silver layer, a second silver layer over said second chalcogenide glass layer, and a conductive adhesion layer over said a second silver layer.
摘要翻译：本发明涉及用于提供具有改进的数据保持和切换特性的电阻可变存储元件的方法和装置。根据本发明的一个实施方案，提供了一种电阻可变存储元件，其在两个玻璃层之间具有至少一个银硒化物层，其中至少一个玻璃层是硫族化物玻璃，优选具有GexSe100-x组成。根据本发明的另一个实施例，提供了一种电阻可变存储元件，其具有在硫属化物玻璃层之间的至少一个硒化银层，并且还具有位于至少一个所述硫族化物玻璃层之上的银层和位于所述硫属化物玻璃上方的导电粘附层银层。根据本发明的另一个实施例，提供一种电阻可变存储元件，其具有第一硫族化物玻璃层，在所述硫族化物玻璃层上方的银层，在所述银层上方的第二硫族化物玻璃层，在所述第二硫族化物上方的第二银层玻璃层和在所述第二银层上的导电粘附层。

50. 发明授权

US07646007B2 Silver-selenide/chalcogenide glass stack for resistance variable memory 有权
标题翻译：用于电阻变量记忆的硒化银/硫族化物玻璃堆叠
公开(公告)号：US07646007B2
公开(公告)日：2010-01-12
申请号：US11585259
申请日：2006-10-24
申请人： Kristy A. Campbell , John T. Moore
发明人： Kristy A. Campbell , John T. Moore
IPC分类号： H01L29/06
CPC分类号： G11C13/0011 , G11C2213/51 , G11C2213/56 , H01L45/085 , H01L45/1233 , H01L45/143 , H01L45/1616 , H01L45/1625
摘要： The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100−x composition.
摘要翻译：本发明涉及用于提供具有改进的数据保持和切换特性的电阻可变存储元件的方法和装置。根据本发明的实施例，提供了一种电阻可变存储元件，其在玻璃层之间具有至少一个硒化银层，其中至少一个玻璃层是硫族化物玻璃，优选具有GexSe100-x组成。

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