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1. 发明授权

US6096660A Method for removing undesirable second oxide while minimally affecting a desirable first oxide 失效
标题翻译：用于去除不期望的第二氧化物同时最小化影响所需的第一氧化物的方法
公开(公告)号：US6096660A
公开(公告)日：2000-08-01
申请号：US915874
申请日：1997-08-21
申请人： David L. Chapek , John T. Moore
发明人： David L. Chapek , John T. Moore
IPC分类号： H01L21/311 , H01L21/314 , H01L21/762 , H01L21/31 , H01L21/76
CPC分类号： H01L21/3144 , H01L21/31111 , H01L21/76202
摘要： The present invention relates generally to removing an undesirable second oxide, while minimally affecting a desirable first oxide, on an integrated circuit. The integrated circuit may be part of a larger system.The second oxide is first converted to another material, such as oxynitride. The other material has differing characteristics, such as etching properties, so that it can then be removed, without substantially diminishing the first oxide.The conversion may be accomplished by heating. Heating may be accomplished by rapid thermal or furnace processing. Subsequently, the other material is removed from the integrated circuit, for example by hot phosphoric etching, so that the desirable first oxide is not substantially affected.
摘要翻译：本发明一般涉及在集成电路上去除不理想的第二氧化物，同时最小程度地影响所需的第一氧化物。集成电路可能是较大系统的一部分。首先将第二氧化物转化为另一种材料，例如氧氮化物。另一种材料具有不同的特性，例如蚀刻性质，使得其可被除去，而基本上不会减少第一氧化物。转化可以通过加热来完成。加热可以通过快速热处理或炉加工来完成。随后，例如通过热磷蚀刻从集成电路中除去另一种材料，使得所需的第一氧化物基本上不受影响。

2. 发明授权

US6051480A Trench isolation for semiconductor devices 失效
标题翻译：半导体器件的沟槽隔离
公开(公告)号：US6051480A
公开(公告)日：2000-04-18
申请号：US993329
申请日：1997-12-18
申请人： John T. Moore , David L. Chapek
发明人： John T. Moore , David L. Chapek
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the non-trench area, similar amounts of material are removed in both the trench area and non-trench area in a subsequent etching process. Consequently, formation of notches and grooves in the semiconductor structure is minimized. A sacrificial oxide layer may be made by depositing a layer of a suitable material on the surface of a semiconductor structure. By depositing a sacrificial oxide layer instead of thermally growing a sacrificial oxide layer, grooves and the notches in the trench areas are filled by the deposited material.
摘要翻译：在蚀刻沟槽隔离结构中，衬垫氧化物或牺牲氧化物可以形成为与沟槽填料基本上相同（或更高）的蚀刻速率。因为沟槽区域中的蚀刻速率基本上类似于（或小于）非沟槽区域中的蚀刻速率，所以在随后的蚀刻工艺中，在沟槽区域和非沟槽区域中去除相似量的材料。因此，半导体结构中的凹口和凹槽的形成最小化。可以通过在半导体结构的表面上沉积合适的材料层来制造牺牲氧化物层。通过沉积牺牲氧化物层而不是热生长牺牲氧化物层，沟槽区域中的凹槽和凹口被沉积的材料填充。

3. 发明授权

US07235856B1 Trench isolation for semiconductor devices 有权
标题翻译：半导体器件的沟槽隔离
公开(公告)号：US07235856B1
公开(公告)日：2007-06-26
申请号：US09496794
申请日：2000-02-02
申请人： John T. Moore , David L. Chapek
发明人： John T. Moore , David L. Chapek
IPC分类号： H01L29/00
CPC分类号： H01L21/76224
摘要： In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the non-trench area, similar amounts of material are removed in both the trench area and non-trench area in a subsequent etching process. Consequently, formation of notches and grooves in the semiconductor structure is minimized. A sacrificial oxide layer may be made by depositing a layer of a suitable material on the surface of a semiconductor structure. By depositing a sacrificial oxide layer instead of thermally growing a sacrificial oxide layer, grooves and the notches in the trench areas are filled by the deposited material.
摘要翻译：在蚀刻沟槽隔离结构中，衬垫氧化物或牺牲氧化物可以形成为与沟槽填料基本上相同（或更高）的蚀刻速率。因为沟槽区域中的蚀刻速率基本上类似于（或小于）非沟槽区域中的蚀刻速率，所以在随后的蚀刻工艺中，在沟槽区域和非沟槽区域中去除相似量的材料。因此，半导体结构中的凹口和凹槽的形成最小化。可以通过在半导体结构的表面上沉积合适的材料层来制造牺牲氧化物层。通过沉积牺牲氧化物层而不是热生长牺牲氧化物层，沟槽区域中的凹槽和凹口被沉积的材料填充。

4. 发明授权

US06214697B1 Trench isolation for semiconductor devices 有权
标题翻译：半导体器件的沟槽隔离
公开(公告)号：US06214697B1
公开(公告)日：2001-04-10
申请号：US09560416
申请日：2000-04-27
申请人： John T. Moore , David L. Chapek
发明人： John T. Moore , David L. Chapek
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the non-trench area, similar amounts of material are removed in both the trench area and non-trench area in a subsequent etching process. Consequently, formation of notches and grooves in the semiconductor structure is minimized. A sacrificial oxide layer may be made depositing a layer of a suitable material on the surface of a semiconductor structure. By depositing sacrificial oxide layer instead of thermally growing a sacrificial oxide layer, grooves and the notches in the trench areas are filled by the deposited material.
摘要翻译：在蚀刻沟槽隔离结构中，衬垫氧化物或牺牲氧化物可以形成为与沟槽填料基本上相同（或更高）的蚀刻速率。因为沟槽区域中的蚀刻速率基本上类似于（或小于）非沟槽区域中的蚀刻速率，所以在随后的蚀刻工艺中，在沟槽区域和非沟槽区域中去除相似量的材料。因此，半导体结构中的凹口和凹槽的形成最小化。可以使牺牲氧化物层在半导体结构的表面上沉积合适的材料层。通过沉积牺牲氧化物层而不是热生长牺牲氧化物层，沟槽区域中的凹槽和凹口被沉积的材料填充。

5. 发明授权

US06891245B2 Integrated circuit formed by removing undesirable second oxide while minimally affecting a desirable first oxide 失效
标题翻译：通过去除不期望的第二氧化物而形成的集成电路，同时最小程度地影响期望的第一氧化物
公开(公告)号：US06891245B2
公开(公告)日：2005-05-10
申请号：US09563078
申请日：2000-04-24
申请人： David L. Chapek , John T. Moore
发明人： David L. Chapek , John T. Moore
IPC分类号： H01L21/311 , H01L21/314 , H01L21/762 , H01L29/00
CPC分类号： H01L21/3144 , H01L21/31111 , H01L21/76202
摘要： The present invention relates generally to removing an undesirable second oxide, while minimally affecting a desirable first oxide, on an integrated circuit. The integrated circuit may be part of a larger system.The second oxide is first converted to another material, such as oxynitride. The other material has differing characteristics, such as etching properties, so that it can then be removed, without substantially diminishing the first oxide.The conversion may be accomplished by heating. Heating may be accomplished by rapid thermal or furnace processing. Subsequently, the other material is removed from the integrated circuit, for example by hot phosphoric etching, so that the desirable first oxide is not substantially affected.
摘要翻译：本发明一般涉及在集成电路上去除不理想的第二氧化物，同时最小程度地影响所需的第一氧化物。集成电路可能是较大系统的一部分。首先将第二氧化物转化为另一种材料，例如氧氮化物。另一种材料具有不同的特性，例如蚀刻性质，使得其可以被除去而基本上不会减少第一氧化物。转化可以通过加热来完成。加热可以通过快速热处理或炉加工完成。随后，例如通过热磷蚀刻从集成电路中除去另一种材料，使得所需的第一氧化物基本上不受影响。

6. 发明授权

US08058130B2 Method of forming a nitrogen-enriched region within silicon-oxide-containing masses 有权
标题翻译：在含氧化硅的质量块内形成富氮区的方法
公开(公告)号：US08058130B2
公开(公告)日：2011-11-15
申请号：US12196988
申请日：2008-08-22
申请人： Gurtej S. Sandhu , John T. Moore , Neal R. Rueger
发明人： Gurtej S. Sandhu , John T. Moore , Neal R. Rueger
IPC分类号： H01L21/00
CPC分类号： H01L21/02332 , H01L21/0234 , H01L21/265 , H01L21/28061 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.
摘要翻译：本发明包括将氮掺入含氧化硅的层中的方法。将含氧化硅的层暴露于含氮等离子体中以将氮引入层中。氮气随后在层内热退火以将至少一些氮与硅结合在层内。本发明还包括形成晶体管的方法。在半导体衬底上形成栅氧化层。栅氧化层包括二氧化硅。将栅极氧化层暴露于含氮等离子体中以将氮引入层中，并且在暴露期间该层保持在小于或等于400℃。随后，层内的氮被热退火以将至少大部分氮与硅结合。在栅极氧化物层上形成至少一个导电层。源极/漏极区域形成在半导体衬底内，并且通过至少一个导电层彼此门控连接。本发明还包括晶体管结构。

7. 发明申请

US20080225579A1 MEMORY ARCHITECTURE AND METHOD OF MANUFACTURE AND OPERATION THEREOF 有权
标题翻译：存储器结构及其制造和操作方法
公开(公告)号：US20080225579A1
公开(公告)日：2008-09-18
申请号：US12110532
申请日：2008-04-28
申请人： John T. Moore , Terry L. Gilton
发明人： John T. Moore , Terry L. Gilton
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00 , H01L21/00
CPC分类号： G11C13/003 , G11C5/063 , G11C7/18 , G11C11/4097 , G11C13/0011 , G11C13/004 , G11C2213/75 , G11C2213/76 , G11C2213/79 , H01L27/0203 , H01L27/105 , H01L27/1052
摘要： An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable conductive access memory elements. The architecture in one exemplary embodiment has a pair of semi-volatile or non-volatile memory elements which selectively share a bit line through respective first electrodes and access transistors controlled by respective word lines. The memory elements each have a respective second electrode coupled thereto which in cooperation with the bit line access transistors and first electrode, serves to apply read, write and erase signals to the memory element.
摘要翻译：一种架构及其形成和操作方法，其包含半易失性或非易失性存储器元件的高密度存储器阵列，包括但不限于可编程导电存取存储器元件。一个示例性实施例中的架构具有一对半挥发性或非易失性存储器元件，其通过相应的第一电极和由相应字线控制的存取晶体管选择性地共享位线。存储元件各自具有耦合到其上的相应的第二电极，其与位线存取晶体管和第一电极协作，用于向存储元件施加读取，写入和擦除信号。

8. 发明授权

US07385868B2 Method of refreshing a PCRAM memory device 有权
标题翻译：刷新PCRAM存储器件的方法
公开(公告)号：US07385868B2
公开(公告)日：2008-06-10
申请号：US11128177
申请日：2005-05-13
申请人： John T. Moore , Terry L. Gilton , Kristy A. Campbell
发明人： John T. Moore , Terry L. Gilton , Kristy A. Campbell
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/406 , G11C11/40622 , G11C13/0004 , G11C13/0011 , G11C13/0033 , G11C16/3431 , G11C2211/4065 , G11C2211/4068 , G11C2213/79
摘要： A method for refreshing PCRAM cells programmed to a low resistance state and entire arrays of PCRAM cells uses a simple refresh scheme which does not require separate control and application of discrete refresh voltages to the PCRAM cells in an array. Specifically, the array structure of a PCRAM device is constructed to allow leakage current to flow through each programmed cell in the array to refresh the programmed state. In one embodiment, the leakage current flows across the access device between the anode of the memory element and the bit line to which the cell is connected, for each memory cell in the array which has been programmed to the low resistance state. In another embodiment, the leakage current flows to the programmed cells through a doped substrate or doped regions of a substrate on which each cell is formed. An entire array is refreshed simultaneously by forming each memory element in the array to have one common anode formed as a single cell plate for the array. Only PCRAM cells in the array written to the low resistance state are refreshed by the controlled leakage current, whereas cells in the high resistance state are not affected by the refresh operation.
摘要翻译：用于刷新编程为低电阻状态的PCRAM细胞的方法和PCRAM细胞的整个阵列使用简单的刷新方案，其不需要单独控制并且向阵列中的PCRAM细胞施加离散的刷新电压。具体地，构建PCRAM器件的阵列结构以允许漏电流流过阵列中的每个编程单元以刷新编程状态。在一个实施例中，针对已经被编程为低电阻状态的阵列中的每个存储器单元，漏电流在存储元件的阳极和单元连接的位线之间流过访问设备。在另一个实施例中，漏电流通过其上形成有每个单元的衬底的掺杂衬底或掺杂区流动到编程单元。通过在阵列中形成每个存储元件以使一个共同的阳极形成为阵列的单个单元板，整个阵列同时刷新。写入低电阻状态的阵列中只有PCRAM单元被控制的漏电流刷新，而高电阻状态下的单元不受刷新操作的影响。

9. 发明授权

US07199444B2 Memory device, programmable resistance memory cell and memory array 有权
标题翻译：存储器件，可编程电阻存储单元和存储器阵列
公开(公告)号：US07199444B2
公开(公告)日：2007-04-03
申请号：US11219742
申请日：2005-09-07
申请人： John T. Moore , Terry L. Gilton
发明人： John T. Moore , Terry L. Gilton
IPC分类号： H01L29/12
CPC分类号： H01L45/04 , H01L27/101 , H01L28/24 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1658 , H01L45/1675
摘要： A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices. In one implementation, a non-volatile resistance variable device in a highest resistance state for a given ambient temperature and pressure includes a resistance variable chalcogenide material having metal ions diffused therein. Opposing first and second electrodes are received operatively proximate the resistance variable chalcogenide material. At least one of the electrodes has a conductive projection extending into the resistance variable chalcogenide material.
摘要翻译：金属掺杂硫族化物材料的方法包括在衬底上形成金属。在金属上形成硫族化物材料。通过硫属化物材料对金属进行辐射，有效地在金属和硫族化物材料的界面处破坏硫族化物材料的硫族化物键，并将至少一些金属向外扩散到硫族化物材料中。金属掺杂硫族化物材料的方法包括用硫族化物材料包围突出的金属块的暴露的外表面。通过硫族化物材料将辐射照射到突出金属质量块上，有效地在突出的金属质量外表面的界面处破坏硫族化物材料的硫族化物键，并将至少一些突出的金属块向外扩散到硫族化物材料中。在某些方面，上述实施方式被并入形成非易失性电阻可变器件的方法中。在一个实施方案中，对于给定的环境温度和压力，最高电阻状态的非易失性电阻可变器件包括在其中扩散有金属离子的电阻变化硫属化物材料。反向的第一和第二电极在电阻可变硫属化物材料上可操作地接收。至少一个电极具有延伸到电阻可变硫族化物材料中的导电突起。

10. 发明授权

US07157778B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US07157778B2
公开(公告)日：2007-01-02
申请号：US11018848
申请日：2004-12-20
申请人： John T. Moore
发明人： John T. Moore
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L21/823462 , H01L21/3145 , H01L21/31612
摘要： The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the substrate. After the nitrogen-containing layer is formed, an oxide region is grown from at least some of the substrate. The nitrogen of the nitrogen-containing layer is dispersed within the oxide region. The invention also encompasses a method of forming a pair of transistors associated with a semiconductor substrate. A substrate is provided. A first region of the substrate is defined, and additionally a second region of the substrate is defined. A first oxide region is formed which covers at least some of the first region of the substrate, and which does not cover any of the second region of the substrate. A nitrogen-comprising layer is formed across at least some of the first oxide region and across at least some of the second region of the substrate. After the nitrogen-comprising layer is formed, a second oxide region is grown from the second region of the substrate. A first transistor gate is formed over the first oxide region, and a second transistor gate is formed over the second oxide region.
摘要翻译：本发明包括在半导体衬底上形成氧化物区域的方法。在至少一些基底上形成含氮层。在形成含氮层之后，从衬底中的至少一些生长氧化物区域。含氮层的氮分散在氧化物区域内。本发明还包括形成与半导体衬底相关联的一对晶体管的方法。提供基板。限定衬底的第一区域，并且另外定义衬底的第二区域。形成第一氧化物区域，其覆盖衬底的第一区域中的至少一些，并且不覆盖衬底的任何第二区域。跨越第一氧化物区域中的至少一些并穿过衬底的至少一些第二区域形成含氮层。在形成含氮层之后，从衬底的第二区域生长第二氧化物区域。在第一氧化物区域上形成第一晶体管栅极，在第二氧化物区域上形成第二晶体管栅极。

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