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41. 发明授权

US06436770B1 Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation 失效
标题翻译：通过使用选择性外延和使用注入的源极/漏极首先形成沟道来控制垂直晶体管的沟道长度的方法
公开(公告)号：US06436770B1
公开(公告)日：2002-08-20
申请号：US09721720
申请日：2000-11-27
申请人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
发明人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
IPC分类号： H01L21332
CPC分类号： H01L29/7827 , H01L29/42356 , H01L29/66666
摘要： A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. Contacts are formed through the interlevel dielectric layer to the doped gate regions, the drain region and the source region.
摘要翻译：一种垂直MOS晶体管的方法，其垂直沟道宽度可以被精确地限定和控制。在衬底中形成隔离区。隔离区限定有效区域。然后，我们在活动区域中形成一个源区域。在有源区域和隔离区域上形成介电层。我们在电介质层上形成阻挡层。我们在屏障层形成一个开口。在开口中形成栅极层。我们在导电层和阻挡层上形成绝缘层。我们通过绝缘层，栅极层和电介质层形成栅极开口以暴露源极区域。栅极电介质隔离物形成在栅极层的侧壁上。然后，我们形成一个填充门开口的导电塞。绝缘层被去除。我们在导电插塞的顶部和侧部形成漏极区，并在栅极层中形成掺杂的栅极区。导电插塞的其余部分包括沟道区域。沟道长度在源极区域的顶部和漏极区域之间。我们在阻挡层，栅极层和导电插塞上形成层间电介质层。通过层间介质层与掺杂栅极区，漏极区和源极区形成触点。

42. 发明授权

US06323125B1 Simplified dual damascene process utilizing PPMSO as an insulator layer 失效
标题翻译：使用PPMSO作为绝缘体层的简化双镶嵌工艺
公开(公告)号：US06323125B1
公开(公告)日：2001-11-27
申请号：US09282065
申请日：1999-03-29
申请人： Choi Pheng Soo , Wye Boon Loh , Lap Chan
发明人： Choi Pheng Soo , Wye Boon Loh , Lap Chan
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/3121 , H01L21/76808 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： Only one photo mask defines the metal trench and via region. The mask blocks the UV light in the trench and via area forming Plasma Polymerized Methylsilane Oxide (PPMSO) in the exposed areas. Two step RIE plasma treatment using chlorine gas and oxygen gas removes the Plasma Polymerized Methylsilane (PPMS) in the trench and via regions. Conductive metal is deposited. A CMP process polishes back both excess metal along with the PPMSO, at a similar rate, to form: conducting metal lines, interconnects, and via contacts without metal dishing.
摘要翻译：只有一个光罩定义了金属沟槽和通孔区域。掩模在暴露的区域中阻挡沟槽中的UV光和形成等离子聚合甲基硅烷氧化物（PPMSO）的通孔区域。使用氯气和氧气的两步RIE等离子体处理在沟槽和通孔区域中除去等离子体聚合甲基硅烷（PPMS）。导电金属被沉积。 CMP工艺以类似的速率抛光多余金属与PPMSO，以形成：导电金属线，互连和通孔触点，而不会金属凹陷。

43. 发明授权

US06313008B1 Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon 失效
标题翻译：使用微加工技术形成气球形STI以去除重掺杂硅的方法
公开(公告)号：US06313008B1
公开(公告)日：2001-11-06
申请号：US09768486
申请日：2001-01-25
申请人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
发明人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a Si damaged or doped first region. The first region is selectively etching to form a hole. The hole is filled with an insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions. The second embodiment differs from the first embodiment by forming a trench in the substrate before the implant. The third embodiment forms a liner in the trench before an isotropic etch of the substrate through the trench.
摘要翻译：本发明描述了形成球形STI沟槽的方法的三个实施例。第一实施例开始于在衬底上形成阻挡层。在阻挡层中形成隔离开口。接下来，通过所述隔离开口将离子注入到所述衬底中，以形成Si损伤或掺杂的第一区域。第一区域是选择性蚀刻以形成孔。孔用绝缘材料填充以形成气球形的浅沟槽隔离（STI）区域。衬底在所述球形浅沟槽隔离（STI）区域之间具有有效区域。第二实施例通过在植入物之前在衬底中形成沟槽而与第一实施例不同。在通过沟槽对衬底进行各向同性蚀刻之前，第三实施例在沟槽中形成衬垫。

44. 发明授权

US06252290B1 Method to form, and structure of, a dual damascene interconnect device 有权
标题翻译：双镶嵌互连装置的形成和结构的方法
公开(公告)号：US06252290B1
公开(公告)日：2001-06-26
申请号：US09425903
申请日：1999-10-25
申请人： Shyue Fong Quek , Ting Cheong Ang , Lap Chan , Sang Yee Loong
发明人： Shyue Fong Quek , Ting Cheong Ang , Lap Chan , Sang Yee Loong
IPC分类号： H01L2900
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76835 , H01L2221/1026
摘要： A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprises the following steps. A first level via photo sensitive dielectric layer is deposited and exposed over a semiconductor structure. A first level trench photo sensitive dielectric layer is deposited and exposed over the first via photo sensitive dielectric layer. The exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers are patterned and etched to form a first level dual damascene opening. The first level dual damascene opening comprises an integral first level via and metal line openings. A first level metal layer is deposited over the first level trench photo sensitive dielectric layer, filling the first level dual damascene opening. The first level metal layer is planarized to form at least one first level dual damascene interconnect having a first level horizontal metal line and a first level vertical via stack. The above steps are repeated n-1 times to form n-1 more dual damascene interconnects over the first level dual damascene interconnect where n is the number of interconnect levels desired. A passivation layer is deposited and patterned over the nth metal dual damascene interconnect layer to form openings in the passivation layer. The n number of via photo sensitive dielectric and trench photo sensitive dielectric layers are stripped and removed beneath the passivation layer openings and between the plurality of dual damascene structures wherein the portion of the via photo sensitive dielectric underneath the horizontal metal lines of the stripped trench photo sensitive dielectric layers remains.
摘要翻译：一种在半导体器件中制造双镶嵌互连结构的方法，包括以下步骤。通过光敏电介质层的第一级沉积并暴露在半导体结构上。第一级沟槽光电介质层被沉积并暴露在第一通孔光敏介电层上。通过光敏电介质和沟槽光敏电介质层曝光的第一级被图案化和蚀刻以形成第一级双镶嵌开口。第一级双镶嵌开口包括集成的第一级通孔和金属线开口。第一级金属层沉积在第一级沟槽光敏介电层上，填充第一级双镶嵌开口。第一级金属层被平坦化以形成具有第一级水平金属线和第一级垂直通孔叠层的至少一个第一级双镶嵌互连。上述步骤重复n-1次，以在第一级双镶嵌互连上形成n-1个双镶嵌互连，其中n是所需的互连级数。在第n个金属双镶嵌互连层上沉积并图案化钝化层，以在钝化层中形成开口。在钝化层开口之下和多个双镶嵌结构之间剥离并除去n个通孔光敏电介质层和沟槽光敏介电层，其中通过光敏电介质的部分在剥离的沟槽照片的水平金属线下方保持敏感的电介质层。

45. 发明授权

US06180501B2 Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process 失效
标题翻译：制造二分之一微米自对准钛硅化物工艺的双多晶硅栅极结构的方法
公开(公告)号：US06180501B2
公开(公告)日：2001-01-30
申请号：US09418036
申请日：1999-10-14
申请人： Kin-Leong Pey , Chaw Sing Ho , Lap Chan
发明人： Kin-Leong Pey , Chaw Sing Ho , Lap Chan
IPC分类号： H01L213205
CPC分类号： H01L29/6659 , H01L21/28035 , H01L21/28052 , H01L21/28518 , H01L29/4925 , H01L29/4933 , H01L29/66545
摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for minimizing the localized mechanical stress problems that can occur when silicided polysilicon gates are used to fabricate narrow channel CMOS devices. The invention addresses the avoidance of typical stress-induced problems in polysilicon gates, such as non-uniform silicide (including bowing, thinning edges, etc.) and voids, which are becoming increasingly worse as gate lengths continue to be reduced. The key to this invention is to spread the highly detrimental mechanical stresses, in narrow silicided gates, over a larger vertical surface area. This is accomplished by using a thin/thick double polysilicon stack for the gate, whereby, the lower thin polysilicon gate layer is not silicided and the upper thick polysilicon layer is subsequently silicided. An insulating layer is used to prevent silicidation of the lower thin polysilicon gate, during silicidation of active source-drain regions. The same insulating layer is also used to avoid another cause of mechanical stress, by protecting the surface grain boundaries of the lower thin polysilicon gate layer from being stuffed with polymer during the dry etching used for spacer formation. The tall stacked gate structure allows the silicide-induced stresses to be more safely located farther away from the active devices.
摘要翻译：本发明涉及集成电路器件的制造，更具体地说，涉及一种使硅化多晶硅栅极用于制造窄沟道CMOS器件时可能出现的局部机械应力问题最小化的方法。本发明解决了避免多晶硅栅极中的典型的应力引起的问题，例如不均匀的硅化物（包括弯曲，变薄边缘等）和空隙，随着栅极长度的不断减小，这些问题变得越来越严重。本发明的关键是在狭窄的硅化物栅极中，在较大的垂直表面积上传播高度有害的机械应力。这是通过使用用于栅极的薄/厚双重多晶硅堆叠实现的，由此，下部薄多晶硅栅极层不被硅化，并且随后硅化上部厚多晶硅层。在有源源极 - 漏极区域的硅化期间，使用绝缘层来防止下部薄多晶硅栅极的硅化。同样的绝缘层也用于通过在用于间隔物形成的干蚀刻期间保护下部薄多晶硅栅极层的表面晶界不被聚合物填充而避免机械应力的另一个原因。高堆叠栅极结构允许硅化物引起的应力更安全地远离有源器件。

46. 发明授权

US6143598A Method of fabrication of low leakage capacitor 失效
标题翻译：低漏电容器的制造方法
公开(公告)号：US6143598A
公开(公告)日：2000-11-07
申请号：US246893
申请日：1999-02-08
申请人： John Elmslie Martin , Lap Chan , John Leonard Sudijono , Ting Cheong Ang
发明人： John Elmslie Martin , Lap Chan , John Leonard Sudijono , Ting Cheong Ang
IPC分类号： H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242
CPC分类号： H01L28/40 , H01L28/60 , H01L21/3144 , H01L21/31604 , H01L27/10852
摘要： A capacitor element of a semiconductor device used for high density semiconductor circuits is formed by the steps of forming the bottom plate of the capacitor, submitting the top of the bottom plate to plasma treatment in an oxidizing medium where nitrogen and oxygen are present, depositing a dielectric layer and submitting the top of the dielectric layer to plasma treatment in an oxidizing medium where nitrogen and oxygen are present. Various materials are used for the plasma treatment in an oxidizing medium where nitrogen and oxygen are present. While the present invention uses amorphous silicon as the dielectric material, plasma treatment in an oxidizing medium where nitrogen and oxygen are present can readily applied to a number of other dielectric materials. The objective in constructing capacitors for semiconductor circuits is to reduce the thickness of the dielectric material as much as possible and use a dielectric material for the dielectric which has a high dielectric constant, this increases the value of the capacitor electrical charge which can be carried by the capacitor. The objective of the present invention is to eliminate the leakage current between the plates of a capacitor so that the capacitor can maintain a high voltage between the top and the bottom plate.
摘要翻译：用于高密度半导体电路的半导体器件的电容器元件是通过形成电容器的底板的步骤形成的，将底板的顶部在存在氮和氧的氧化介质中进行等离子体处理，介电层，并将介电层的顶部在存在氮和氧的氧化介质中进行等离子体处理。在存在氮和氧的氧化介质中使用各种材料进行等离子体处理。虽然本发明使用非晶硅作为介电材料，但在存在氮和氧的氧化介质中的等离子体处理可以容易地应用于许多其它电介质材料。用于半导体电路构造电容器的目的是尽可能地减小电介质材料的厚度，并且使用具有高介电常数的电介质的介电材料，这增加了电容器电荷的值电容器。本发明的目的是消除电容器板之间的漏电流，使得电容器能够在顶板和底板之间保持高电压。

47. 发明授权

US6140237A Damascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layer 有权
标题翻译：用于形成由绝缘层中的阻挡层隔离的铜连接器的共面顶表面的镶嵌工艺
公开(公告)号：US6140237A
公开(公告)日：2000-10-31
申请号：US294048
申请日：1999-04-19
申请人： Lap Chan , Jia Zhen Zheng
发明人： Lap Chan , Jia Zhen Zheng
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76843 , H01L23/53238 , H01L2924/0002
摘要： A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
摘要翻译：描述了在集成电路中制造铜互连的结构和方法。该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。通过两个阻挡层防止铜从连接器的扩散。一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。抛光。由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

48. 发明授权

US5948700A Method of planarization of an intermetal dielectric layer using chemical mechanical polishing 失效
标题翻译：使用化学机械抛光对金属间电介质层进行平面化的方法
公开(公告)号：US5948700A
公开(公告)日：1999-09-07
申请号：US650694
申请日：1996-05-20
申请人： Jia Zhen Zheng , Lap Chan
发明人： Jia Zhen Zheng , Lap Chan
IPC分类号： H01L21/3105 , H01L21/306
CPC分类号： H01L21/31053
摘要： A method of planarizing integrated circuit wafers using chemical mechanical polishing with an automatic end point and without using an etchback step. An electrode pattern is formed in a layer of soft metal, such as Al/Cu/Si, capped with a layer of hard metal such as tungsten. A layer of first oxide, a layer of spin on glass, and a layer of second oxide are formed over the electrode pattern. The layer of first oxide, the layer of spin on glass, and the layer of second oxide are then planarized using chemical mechanical polishing. The hard metal cap on the electrode pattern can not be removed by the chemical mechanical polishing and forms an automatic end point. The electric current powering the motor driving the chemical mechanical polishing changes when the hard metal cap is reached and this change can be used to detect the end point.
摘要翻译：使用具有自动终点的化学机械抛光并且不使用回蚀步骤来平面化集成电路晶片的方法。电极图案形成在诸如Al / Cu / Si的软金属层中，其被诸如钨的硬金属层覆盖。在电极图案之上形成第一氧化物层，玻璃上的自旋层和第二氧化物层。然后使用化学机械抛光使第一氧化物层，玻璃上的自旋层和第二氧化物层平坦化。电极图案上的硬金属盖不能通过化学机械抛光去除并形成自动终点。驱动化学机械抛光的电机的电流在达到硬金属帽时发生变化，并且可以使用该变化来检测终点。

49. 发明授权

US5900672A Barrier layer 失效
标题翻译：铜互连与顶部阻挡层
公开(公告)号：US5900672A
公开(公告)日：1999-05-04
申请号：US876915
申请日：1997-06-16
申请人： Lap Chan , Jia Zhen Zheng
发明人： Lap Chan , Jia Zhen Zheng
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76834 , H01L21/76843 , H01L23/53238 , H01L2924/0002
摘要： A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
摘要翻译：描述了在集成电路中制造铜互连的结构和方法。该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。通过两个阻挡层防止铜从连接器的扩散。一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。抛光。由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

50. 发明授权

US5808855A Stacked container capacitor using chemical mechanical polishing 失效
标题翻译：堆放容器电容器采用化学机械抛光
公开(公告)号：US5808855A
公开(公告)日：1998-09-15
申请号：US730009
申请日：1996-10-11
申请人： Lap Chan , Yeow Meng Teo
发明人： Lap Chan , Yeow Meng Teo
IPC分类号： H01L21/02 , H01L21/768 , H01L27/06 , H01L27/108 , H01G4/06
CPC分类号： H01L28/40 , H01L21/76895 , H01L27/0629 , H01L27/108 , H01L28/60 , H01L28/82 , H01L28/90
摘要： A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer. Finally, the filled isotropically etched aperture is planarized until there is exposed a flange of the first polysilicon layer formed into the ledge.
摘要翻译：一种用于形成集成电路内使用的层叠容器电容器的方法。连续形成在半导体衬底上的是第一电介质层，第二电介质层和图案化掩模层。在各向同性蚀刻工艺中，第一介电层比第二介电层慢。通过使用图案化掩模层作为掩模的各向异性蚀刻工艺，至少部分地蚀刻孔，穿过第一介电层。通过使用图案化掩模层作为掩模的各向同性蚀刻工艺，蚀刻第二介电层以产生形成在第一介电层上方并在图案化掩模层下方的凸缘。然后去除图案化的掩模层。然后形成各向异性和各向异性蚀刻的孔径是第一多晶硅层，第三介电层和第二多晶硅层。最后，填充的各向同性蚀刻的孔被平坦化，直到暴露出形成在凸缘中的第一多晶硅层的凸缘。

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