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1. 发明授权

US5895264A Method for forming stacked polysilicon 失效
标题翻译：堆叠多晶硅的形成方法
公开(公告)号：US5895264A
公开(公告)日：1999-04-20
申请号：US902755
申请日：1997-07-30
申请人： Yeow Meng Teo
发明人： Yeow Meng Teo
IPC分类号： H01L21/768 , H01L23/485 , H01L23/522 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76805 , H01L23/5226 , H01L2924/0002
摘要： An improved and new method for forming stacked polysilicon contacts for use in multilevel conducting interconnection wiring in semiconductor integrated circuits has been developed. The polysilicon contacts are self-aligned between wiring levels and the fabrication process results in a substantially planar top insulating layer surface.
摘要翻译：已经开发了用于形成用于半导体集成电路中的多电平导电互连布线的堆叠多晶硅触点的改进和新的方法。多晶硅触点在布线层之间自对准，并且制造工艺导致基本平坦的顶部绝缘层表面。

2. 发明授权

US06368900B1 Method of fabricating an antifuse element 有权
标题翻译：制造反熔丝元件的方法
公开(公告)号：US06368900B1
公开(公告)日：2002-04-09
申请号：US09501374
申请日：2000-02-11
申请人： John Prasao Kenkaraseril , Madhusudan Mukhopadhyay , Qi Dong Xiang , Yeow-Meng Teo
发明人： John Prasao Kenkaraseril , Madhusudan Mukhopadhyay , Qi Dong Xiang , Yeow-Meng Teo
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A process for forming an amorphous silicon, antifuse element, on an underlying, raised tungsten plug structure, has been developed. The process features the recessing of the insulator layer, in which the tungsten plug structure resides, resulting in a raised portion of a tungsten plug structure. Conductive spacers are then formed on the exposed sides of the raised portion of the tungsten plug structure, resulting in smooth edges, at the perophery of the raised tungsten plug structure. An amorphous silicon layer is then deposited and defined to create the amorphous silicon, antifuse element, on the underlying raised tungsten plug structure, smoothed via the addition of the conductive, sidewall spacers. The use of the underlying, smooth, raised tungsten plug structure, alleviates excessive current crowding, presnet at the edges of the raised tungsten plug structure, during a high voltage pulsing procedure, performed to the overlying antifuse element.
摘要翻译：已经开发了用于在下面的凸起的钨插塞结构上形成非晶硅，反熔丝元件的工艺。该方法的特征在于钨插塞结构所在的绝缘体层的凹陷，导致钨插塞结构的凸起部分。然后，在钨插头结构的凸起部分的暴露侧上形成导电间隔物，从而在凸起的钨插头结构的多孔处形成光滑的边缘。然后沉积和限定非晶硅层以在下面的隆起的钨插塞结构上产生非晶硅，反熔丝元件，通过添加导电侧壁间隔物而平滑化。在高电压脉冲过程中，使用底层的，平滑的，提升的钨插头结构，减轻过度的电流拥挤，在升高的钨插塞结构的边缘处，对上覆的反熔丝元件执行。

3. 发明授权

US5808855A Stacked container capacitor using chemical mechanical polishing 失效
标题翻译：堆放容器电容器采用化学机械抛光
公开(公告)号：US5808855A
公开(公告)日：1998-09-15
申请号：US730009
申请日：1996-10-11
申请人： Lap Chan , Yeow Meng Teo
发明人： Lap Chan , Yeow Meng Teo
IPC分类号： H01L21/02 , H01L21/768 , H01L27/06 , H01L27/108 , H01G4/06
CPC分类号： H01L28/40 , H01L21/76895 , H01L27/0629 , H01L27/108 , H01L28/60 , H01L28/82 , H01L28/90
摘要： A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer. Finally, the filled isotropically etched aperture is planarized until there is exposed a flange of the first polysilicon layer formed into the ledge.
摘要翻译：一种用于形成集成电路内使用的层叠容器电容器的方法。连续形成在半导体衬底上的是第一电介质层，第二电介质层和图案化掩模层。在各向同性蚀刻工艺中，第一介电层比第二介电层慢。通过使用图案化掩模层作为掩模的各向异性蚀刻工艺，至少部分地蚀刻孔，穿过第一介电层。通过使用图案化掩模层作为掩模的各向同性蚀刻工艺，蚀刻第二介电层以产生形成在第一介电层上方并在图案化掩模层下方的凸缘。然后去除图案化的掩模层。然后形成各向异性和各向异性蚀刻的孔径是第一多晶硅层，第三介电层和第二多晶硅层。最后，填充的各向同性蚀刻的孔被平坦化，直到暴露出形成在凸缘中的第一多晶硅层的凸缘。

4. 发明授权

US06362102B1 Method of forming top metal contact to antifuse 有权
标题翻译：形成顶部金属接触到反熔丝的方法
公开(公告)号：US06362102B1
公开(公告)日：2002-03-26
申请号：US09472415
申请日：1999-12-27
申请人： Say Gut Piew , Madhusudan Mukhopadhyay , Yeow Meng Teo
发明人： Say Gut Piew , Madhusudan Mukhopadhyay , Yeow Meng Teo
IPC分类号： H01L21302
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a self-aligned antifuse cell is described. An antifuse is provided overlying a metal plug in an insulating layer on a semiconductor substrate. A dielectric layer is deposited overlying the antifuse. The dielectric layer is etched to form dielectric spacers on the sidewalls of the antifuse. A top metal layer is deposited overlying the antifuse and dielectric spacers and patterned to complete the antifuse cell in an integrated circuit device.
摘要翻译：描述了制造自对准反熔丝电池的方法。在半导体衬底上的绝缘层中的金属插头上设置反熔丝。沉积在反熔丝上的电介质层。蚀刻电介质层以在反熔丝的侧壁上形成电介质间隔物。顶部金属层沉积在反熔丝和电介质间隔物上，并被图案化以在集成电路器件中完成反熔丝电池。

5. 发明授权

US5970374A Method for forming contacts and vias with improved barrier metal step-coverage 失效
标题翻译：用于形成具有改进的屏障金属步骤覆盖的触点和通孔的方法
公开(公告)号：US5970374A
公开(公告)日：1999-10-19
申请号：US734065
申请日：1996-10-18
申请人： Yeow Meng Teo
发明人： Yeow Meng Teo
IPC分类号： H01L21/768 , H01L21/311 , H01L21/461
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76846 , H01L21/76877
摘要： A method is described for overcoming the non-conformity and poor step coverage incurred when materials such as metals and barrier materials are deposited into contact or via openings by physical-vapor-deposition (PVD) techniques such as sputtering and evaporation. Conventional PVD deposition into a vertical walled opening results in the formations of cusps along the walls at the mouth of the opening. These cusps obstruct the material stream into the depth of the opening, resulting in inadequate coverage at the base of the opening particularly at the corners. This increases the chance of failure of the barrier material resulting in a reliability exposure. In addition, the cusps, if not removed, cause the formation of voids in subsequently deposited conductive plugs. The invention teaches the insulative layer, wherein the openings are formed, to be deposited to a greater thickness than required by the design. The openings are then formed and filled with a spin-on-glass. The insulative layer is then polished to the design thickness, removing the cusps. The spin-on-glass, which protects the openings from damage and contamination during polishing, is removed and an adhesion layer is applied prior to the deposition of the conductive material of the contact or via.
摘要翻译：描述了一种克服当金属和阻隔材料等材料沉积接触或通过诸如溅射和蒸发之类的物理气相沉积（PVD）技术的开口的不合格和差的步骤覆盖的方法。传统的PVD沉积成垂直的开口导致沿着开口处的壁的尖端的形成。这些尖端阻塞材料流进入开口的深度，导致在开口底部，特别是在角落处的覆盖不充分。这增加了屏障材料故障的可能性导致可靠性暴露。另外，如果没有去除，则在随后沉积的导电塞中形成空隙。本发明教导了形成开口的绝缘层被沉积成比设计所要求的厚度更大的厚度。然后形成开口并用旋涂玻璃填充。然后将绝缘层抛光至设计厚度，去除尖端。在抛光期间保护开口免受损伤和污染的旋涂玻璃被去除，并且在沉积接触件或通孔的导电材料之前施加粘附层。

6. 发明授权

US10529894B2 Contact etching and metallization for improved LED device performance and reliability 有权
公开(公告)号：US10529894B2
公开(公告)日：2020-01-07
申请号：US15777255
申请日：2016-11-14
申请人： David Chong , Yeow-Meng Teo
发明人： David Chong , Yeow-Meng Teo
IPC分类号： H01L33/38 , H01L33/44 , H01L33/46 , H01L33/40 , H01L33/06
摘要： A light emitting device includes a vertical via through the P-type semiconductor layer and the active layer. Using a vertical via reduces quantum well damage, allows shortening of P-N spacing, and allows increased reflective area. A dielectric structure is formed in the via to provide a sloped wall that extends to an upper surface of the device. Another dielectric layer covers the upper surface and the sloped wall, and provides select contacts to the semiconductor layers. A metal layer is subsequently applied. Because the dielectric layers provide a continuous slope from the surface of the device, the metal layer does not include a vertical drop. Because the active layer does not extend into the via, the contact to the N-type semiconductor layer may be situated closer to the wall of the via, increasing the area available for a reflective layer.

7. 发明授权

US06607993B1 Method using ultraviolet radiation for integrated circuit manufacturing 有权
标题翻译：使用紫外线辐射进行集成电路制造的方法
公开(公告)号：US06607993B1
公开(公告)日：2003-08-19
申请号：US10224061
申请日：2002-08-19
申请人： Ronald Dickinson , Yeow Meng Teo , Dong Xiang Qi , Rajan Rajgopal
发明人： Ronald Dickinson , Yeow Meng Teo , Dong Xiang Qi , Rajan Rajgopal
IPC分类号： H01L214763
CPC分类号： H01L21/28194 , H01L21/28176 , H01L21/76838
摘要： A method is provided for manufacturing an integrated circuit including a substrate with a gate layer and a gate dielectric provided on the substrate. The gate layer is formed into a gate using a process that imposes a charge in the gate dielectric. The substrate, gate, and gate dielectric are irradiated to discharge the charge across the gate dielectric.
摘要翻译：提供了一种用于制造集成电路的方法，该集成电路包括具有栅极层的基板和设置在基板上的栅极电介质。使用在栅极电介质中施加电荷的工艺将栅极层形成为栅极。照射衬底，栅极和栅极电介质以在栅极电介质上排出电荷。

8. 发明授权

US06306721B1 Method of forming salicided poly to metal capacitor 有权
标题翻译：形成水银多金属电容器的方法
公开(公告)号：US06306721B1
公开(公告)日：2001-10-23
申请号：US09808926
申请日：2001-03-16
申请人： Yeow Meng Teo , Madhusudan Mukhopadhyay , Heng Jee Kiat
发明人： Yeow Meng Teo , Madhusudan Mukhopadhyay , Heng Jee Kiat
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L28/60
摘要： A new method is provided for the creation of a salicided polysilicon capacitor. A salicided layer of polysilicon is created as the lower plate of a salicided polysilicon capacitor over the surface of a field isolation region. A layer of silicon nitride is deposited over the field oxide isolation region including the surface of the salicided polysilicon layer. A layer of TEOS is deposited over the surface of the layer of silicon nitride, a layer if titanium nitride is deposited over the surface of the layer of TEOS. The layer of TiN is etched after which the layer of TEOS is etched. The etch of the layer of TEOS is an overetch whereby TEOS is symmetrically removed from underneath the etched layer of TiN, leaving remnants of TEOS in place underneath the etched layer of TiN while at the same time creating air gaps underneath the etched layer of TiN. A layer of silane based oxide is deposited over the surface of the field oxide isolation region including the surface of the etched layer of TiN, thus enclosing the air gaps that have been created underneath the etched layer of TiN. The latter layer of silane based oxide is patterned and etched, forming the upper plate of the salicided polysilicon capacitor. The TEOS remnants remaining in place underneath the etched layer of TiN is part of the dielectric layer of the capacitor.
摘要翻译：提供了一种新的方法来创建一个多晶硅多晶硅电容器。在场隔离区域的表面上形成多晶硅的含水层作为水化多晶硅电容器的下板。在包括水化多晶硅层的表面的场氧化物隔离区域上沉积氮化硅层。一层TEOS沉积在氮化硅层的表面上，如果氮化钛沉积在TEOS层的表面上，则是层。蚀刻TiN层，之后蚀刻TEOS层。 TEOS层的蚀刻是过蚀刻，其中TEOS从TiN的蚀刻层下方对称地移除，在TEN的蚀刻层下方留下TEOS的残留物，同时在TiN的蚀刻层下面形成气隙。在包括TiN蚀刻层的表面的场氧化物隔离区的表面上沉积硅烷基氧化物层，从而包围在TiN的蚀刻层下方产生的气隙。对硅烷基氧化物的后一层进行图案化和蚀刻，形成多晶硅电容器的上层板。保留在TiN蚀刻层下方的TEOS残留物是电容器介质层的一部分。

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