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41. 发明授权

US07495743B2 Immersion optical lithography system having protective optical coating 失效
标题翻译：具有保护性光学涂层的浸没光学光刻系统
公开(公告)号：US07495743B2
公开(公告)日：2009-02-24
申请号：US11163007
申请日：2005-09-30
申请人： Steven J. Holmes , Toshiharu Furukawa , Charles W. Koburger, III , Naim Moumen
发明人： Steven J. Holmes , Toshiharu Furukawa , Charles W. Koburger, III , Naim Moumen
IPC分类号： G03B27/42 , G03B27/52
CPC分类号： G03F7/2041 , G03F7/11 , G03F7/70341 , G03F7/70958
摘要： An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.
摘要翻译：提供了一种浸没光刻系统，其包括可操作以产生具有标称波长的光和光学成像系统的光源。光学成像系统具有从光源到待图案化的制品的光路中的光学元件。光学元件具有适于接触占据面部和制品之间的空间的液体的面。光学元件包括可被液体降解的材料和覆盖面上的可降解材料以保护面部免受液体的保护涂层，保护涂层对于光是透明的，当暴露于光时稳定，并且当稳定时暴露于液体。

42. 发明授权

US07491563B2 Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process 失效
标题翻译： STI填充氧化物的氮化，以防止制造过程中STI填充氧化物的损失
公开(公告)号：US07491563B2
公开(公告)日：2009-02-17
申请号：US11955751
申请日：2007-12-13
申请人： Fred Buehrer , Anthony I. Chou , Toshiharu Furukawa , Renee T Mo
发明人： Fred Buehrer , Anthony I. Chou , Toshiharu Furukawa , Renee T Mo
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/76224 , H01L21/823481
摘要： A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure. The method of forming the STI structure is particularly compatible with standard semiconductor device fabrication processes, including chemical mechanical polishing (CMP), because the method incorporates the use of a pure silicon dioxide STI fill and plasma and thermal nitridation processes to form the oxynitride top layer and oxynitride margin, including the oxynitride corners, of the STI fill.
摘要翻译：一种用于半导体器件的改进的浅沟槽隔离（STI）结构的方法和结构。 STI结构包含STI填充物的氮氧化物顶层。可选地，STI结构包括邻近硅沟槽壁的STI填充的氮氧化物边缘。在硅沟槽壁的上边缘附近的氮氧化物边缘的区域包括与氮氧化物边缘的其它区域相比相对较厚并且含有较高浓度的氮的氧氮化物角。氮氧化物的特征是限制了STI填充高度损失，并且还减少了STI填充物中由于氢氟酸蚀刻和其它制造工艺引起的硅衬底的形成。限制STI填充高度损失和形成纹理改善了STI结构的功能。形成STI结构的方法与包括化学机械抛光（CMP）在内的标准半导体器件制造工艺特别兼容，因为该方法包括使用纯二氧化硅STI填充和等离子体和热氮化工艺来形成氧氮化物顶层和氮氧化物边缘，包括氮氧化物拐角，STI填充。

43. 发明申请

US20090035708A1 LAYER PATTERNING USING DOUBLE EXPOSURE PROCESSES IN A SINGLE PHOTORESIST LAYER 有权
标题翻译：在单个光电层中使用双重曝光过程的层状图
公开(公告)号：US20090035708A1
公开(公告)日：2009-02-05
申请号：US11831099
申请日：2007-07-31
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III
IPC分类号： G03F7/20
CPC分类号： G03F7/2024 , G03F7/38 , G03F7/40 , G03F7/70425
摘要： A structure and a method for forming the same. The method includes providing a structure which includes (a) a to-be-patterned layer, (b) a photoresist layer on top of the to-be-patterned layer wherein the photoresist layer includes a first opening, and (c) a cap region on side walls of the first opening. A first top surface of the to-be-patterned layer is exposed to a surrounding ambient through the first opening. The method further includes performing a first lithography process resulting in a second opening in the photoresist layer. The second opening is different from the first opening. A second top surface of the to-be-patterned layer is exposed to a surrounding ambient through the second opening.
摘要翻译：一种结构及其形成方法。该方法包括提供一种结构，其包括（a）待图案化层，（b）在待图案化层的顶部上的光致抗蚀剂层，其中光致抗蚀剂层包括第一开口，和（c）帽区域在第一开口的侧壁上。待图案化层的第一顶表面通过第一开口暴露于周围环境。该方法还包括执行在光致抗蚀剂层中产生第二开口的第一光刻工艺。第二个开口与第一个开口不同。待图案化层的第二顶表面通过第二开口暴露于周围环境。

44. 发明授权

US07435653B2 Methods for forming a wrap-around gate field effect transistor 有权
标题翻译：形成环绕栅场效应晶体管的方法
公开(公告)号：US07435653B2
公开(公告)日：2008-10-14
申请号：US11735075
申请日：2007-04-13
申请人： Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/78645 , H01L29/78648
摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.
摘要翻译：形成具有环绕，垂直排列的双栅电极的场效应晶体管。从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。第二次回蚀将栅极导体材料的一部分移除第二距离。第一和第二距离之间的差异定义了最终设备的栅极长度。剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

45. 发明申请

US20080224256A1 SEMICONDUCTOR-ON-INSULATOR(SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX) 有权
标题翻译：半导体绝缘体（SOI）结构，包括梯度氮化氧化物（BOX）
公开(公告)号：US20080224256A1
公开(公告)日：2008-09-18
申请号：US12123706
申请日：2008-05-20
申请人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
发明人： Anthony I. Chou , Toshiharu Furukawa , Wilfried Haensch , Zhibin Ren , Dinkar V. Singh , Jeffrey W. Sleight
IPC分类号： H01L23/58 , H01L21/762
CPC分类号： H01L29/78603 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer
摘要翻译：绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间

46. 发明申请

US20080206996A1 SIDEWALL IMAGE TRANSFER PROCESSES FOR FORMING MULTIPLE LINE-WIDTHS 失效
标题翻译：用于形成多个线宽的平面图像传输过程
公开(公告)号：US20080206996A1
公开(公告)日：2008-08-28
申请号：US11680204
申请日：2007-02-28
申请人： Toshiharu Furukawa , John G. Gaudiello , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger
发明人： Toshiharu Furukawa , John G. Gaudiello , Mark Charles Hakey , David Vaclav Horak , Charles William Koburger
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/28123
摘要： A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD
摘要翻译：同时形成多个线宽的方法，其中之一小于使用常规光刻技术可实现的线宽。该方法包括提供在存储层顶部包括存储层和侧壁图像传输（SIT）层的结构。然后，对SIT层进行图案化，形成SIT区域。然后，在存储层的定向蚀刻期间，将SIT区域用作阻挡掩模，产生第一存储区域。然后，SIT区域的侧壁在参考方向上退回退避距离D，导致SIT部分。所述图案化包括光刻工艺。退回距离D小于与光刻工艺相关联的关键尺寸CD。 SIT区域包括参考方向上的第一维W 2和第二维W 3，其中CD

47. 发明申请

US20080157202A1 SOFT ERROR REDUCTION OF CMOS CIRCUITS ON SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION USING BURIED RECOMBINATION CENTERS 有权
标题翻译：使用BURIED重组中心使用混合晶体方位的基板上CMOS电路的软错误减少
公开(公告)号：US20080157202A1
公开(公告)日：2008-07-03
申请号：US11618346
申请日：2006-12-29
申请人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger , Jack A. Mandelman , William Tonti
发明人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger , Jack A. Mandelman , William Tonti
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L29/1083
摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.
摘要翻译：公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。可以形成多个掩埋复合层。可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

48. 发明授权

US07393779B2 Shrinking contact apertures through LPD oxide 失效
标题翻译：通过LPD氧化物收缩接触孔
公开(公告)号：US07393779B2
公开(公告)日：2008-07-01
申请号：US11163786
申请日：2005-10-31
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.
摘要翻译：通过电介质的亚光刻接触孔形成在电介质，硬掩模和含氧化物种子层的堆叠中。通过种子层的初始孔径通过液相沉积接收氧化物沉积，该相沉积选择性地粘附到种子层中的孔的暴露的垂直壁。通过所添加的材料的厚度减小尺寸的亚光刻孔径在硬掩模中限定了减小的孔径。缩小的硬掩模然后限定通过电介质的亚光刻孔。

49. 发明授权

US07368712B2 Y-shaped carbon nanotubes as AFM probe for analyzing substrates with angled topography 有权
标题翻译： Y型碳纳米管作为用于分析具有倾斜的地形的基底的AFM探针
公开(公告)号：US07368712B2
公开(公告)日：2008-05-06
申请号：US11164792
申请日：2005-12-06
申请人： Carol A. Boye , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Carol A. Boye , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： G01N23/00 , G21K7/00
CPC分类号： G01Q60/42 , G01Q70/12
摘要： A Y-shaped carbon nanotube atomic force microscope probe tip and methods comprise a shaft portion; a pair of angled arms extending from a same end of the shaft portion, wherein the shaft portion and the pair of angled arms comprise a chemically modified carbon nanotube, and wherein the chemically modified carbon nanotube is modified with any of an amine, carboxyl, fluorine, and metallic component. Preferably, each of the pair of angled arms comprises a length of at least 200 nm and a diameter between 10 and 200 nm. Moreover, the chemically modified carbon nanotube is preferably adapted to allow differentiation between substrate materials to be probed. Additionally, the chemically modified carbon nanotube is preferably adapted to allow fluorine gas to flow through the chemically modified carbon nanotube onto a substrate to be characterized. Furthermore, the chemically modified carbon nanotube is preferably adapted to chemically react with a substrate surface to be characterized.
摘要翻译： Y型碳纳米管原子力显微镜探针头和方法包括轴部分; 一对成角度的臂，其从所述轴部的同一端延伸，其中所述轴部和所述一对成角度的臂包括化学改性的碳纳米管，并且其中所述化学改性的碳纳米管用胺，羧基，氟，和金属成分。优选地，一对成角度的臂中的每一个包括至少200nm的长度和10和200nm之间的直径。此外，化学改性的碳纳米管优选适于允许待探测的基底材料之间的分化。此外，化学改性的碳纳米管优选适于使氟气通过化学改性的碳纳米管流动到待表征的基底上。此外，化学改性的碳纳米管优选适于与要表征的基材表面发生化学反应。

50. 发明申请

US20080099844A1 MULTIPLE LAYER AND CYRSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE 有权
标题翻译：多层和单层平面定向半导体基板
公开(公告)号：US20080099844A1
公开(公告)日：2008-05-01
申请号：US11969320
申请日：2008-01-04
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
IPC分类号： H01L29/786
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/823807 , H01L27/1203
摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
摘要翻译：绝缘体上半导体衬底及其制造方法。所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向，第一晶体方向与第二晶体方向不同。

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