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41. 发明授权

US07714377B2 Integrated circuits and methods of manufacturing thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US07714377B2
公开(公告)日：2010-05-11
申请号：US11737617
申请日：2007-04-19
申请人： Michael Specht , Nicolas Nagel , Franz Hofmann , Thomas Mikolajick
发明人： Michael Specht , Nicolas Nagel , Franz Hofmann , Thomas Mikolajick
IPC分类号： H01L29/788
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , Y10T29/49117
摘要： Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.
摘要翻译：本发明的实施例涉及具有存储单元布置的集成电路及其制造方法。在本发明的一个实施例中，集成电路具有存储单元布置，其包括沿其纵向方向延伸的翅片结构作为第一方向，包括第一绝缘层，设置在第一绝缘层上方的第一有源区，第二绝缘层设置在所述第一有源区上方的第二有源区，设置在所述第二绝缘层上方的第二有源区，电荷存储层结构，其至少布置在所述鳍结构的至少一个侧壁上，覆盖所述第一有源区的至少一部分，并且至少第二有源区的一部分，以及设置在电荷存储层结构旁边的控制栅。

42. 发明授权

US07521351B2 Method for forming a semiconductor product and semiconductor product 失效
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US07521351B2
公开(公告)日：2009-04-21
申请号：US11172366
申请日：2005-06-30
申请人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
发明人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.
摘要翻译：半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。在其中设置有具有接触孔的第二介质层。接触孔在第一横向具有宽度。该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

43. 发明申请

US20090097317A1 Integrated Circuit Having NAND Memory Cell Strings 有权
标题翻译：具有NAND存储器单元串的集成电路
公开(公告)号：US20090097317A1
公开(公告)日：2009-04-16
申请号：US11872655
申请日：2007-10-15
申请人： Josef Willer , Franz Hofmann , Detlev Richter , Nicolas Nagel
发明人： Josef Willer , Franz Hofmann , Detlev Richter , Nicolas Nagel
IPC分类号： G11C16/00 , H01L21/336 , H01L29/788
CPC分类号： G11C16/0483 , G11C16/0475 , H01L27/115 , H01L27/11565 , H01L27/11568
摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.
摘要翻译：本发明的实施例一般涉及用于制造集成电路的集成电路和方法。在本发明的实施例中，提供了具有存储单元的集成电路。存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区旁边的沟槽。

44. 发明申请

US20080237738A1 Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell arrangement; memory module 审中-公开
标题翻译：集成电路，电池，电池布置，集成电路的制造方法，电池装置的制造方法。内存模块
公开(公告)号：US20080237738A1
公开(公告)日：2008-10-02
申请号：US11728970
申请日：2007-03-27
申请人： Christoph Andreas Kleint , Dirk Manger , Nicolas Nagel , Andreas Taeuber
发明人： Christoph Andreas Kleint , Dirk Manger , Nicolas Nagel , Andreas Taeuber
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/743 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： The present invention relates generally to integrated circuits, a cell, a cell arrangement, a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement and a memory module. In an embodiment of the invention, an integrated circuit having a cell is provided. The cell includes a first source/drain region, a second source/drain region, an active region between the first source/drain region and the second source/drain region, a gate insulating region disposed above the active region, a gate region disposed above the gate insulating region, and at least one metal structure below the first source/drain region or the second source/drain region.
摘要翻译：本发明一般涉及集成电路，单元，单元布置，集成电路的制造方法，单元布置的制造方法和存储器模块。在本发明的实施例中，提供了具有单元的集成电路。电池包括第一源极/漏极区域，第二源极/漏极区域，第一源极/漏极区域和第二源极/漏极区域之间的有源区域，设置在有源区域上方的栅极绝缘区域，栅极绝缘区域以及在第一源极/漏极区域或第二源极/漏极区域下方的至少一个金属结构。

45. 发明申请

US20080237694A1 Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module 审中-公开
标题翻译：集成电路，电池，电池布置，集成电路的制造方法，电池的制造方法，存储器模块
公开(公告)号：US20080237694A1
公开(公告)日：2008-10-02
申请号：US11728960
申请日：2007-03-27
申请人： Michael Specht , Nicolas Nagel , Josef Willer
发明人： Michael Specht , Nicolas Nagel , Josef Willer
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , G11C16/0466 , H01L29/513
摘要： The invention relates to integrated circuits, to a cell, to a cell arrangement, to a method for manufacturing an integrated circuit, to a method for manufacturing a cell, and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a cell, the cell including a low-k dielectric layer, a first high-k dielectric layer disposed above the low-k dielectric layer, a charge trapping layer disposed above the first high-k dielectric layer, and a second high-k dielectric layer disposed above the charge trapping layer.
摘要翻译：本发明涉及集成电路，单元，单元布置，集成电路的制造方法，单元的制造方法以及存储器模块。在本发明的实施例中，提供了具有单元的集成电路，该单元包括低k电介质层，设置在低k电介质层上方的第一高k电介质层，设置在第一高k电介质层和设置在电荷捕获层上方的第二高k电介质层。

46. 发明申请

US20080225587A1 Integrated Circuits, Methods for Manufacturing Integrated Circuits, Integrated Memory Arrays 失效
标题翻译：集成电路，集成电路制造方法，集成存储器阵列
公开(公告)号：US20080225587A1
公开(公告)日：2008-09-18
申请号：US11686211
申请日：2007-03-14
申请人： Nicolas Nagel , Josef Willer
发明人： Nicolas Nagel , Josef Willer
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L21/8221 , H01L27/0688 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L27/11578
摘要： The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays.
摘要翻译：本发明一般涉及集成电路，集成电路的制造方法以及集成存储器阵列。

47. 发明申请

US20070215986A1 Hard mask layer stack and a method of patterning 失效
标题翻译：硬掩模层堆叠和图案化方法
公开(公告)号：US20070215986A1
公开(公告)日：2007-09-20
申请号：US11376645
申请日：2006-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
IPC分类号： H01L23/58 , H01L21/467
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译：用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料碳层顶部和设置在第一层顶部的硅层。图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

48. 发明申请

US20070077748A1 Method for forming a semiconductor product and semiconductor product 审中-公开
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US20070077748A1
公开(公告)日：2007-04-05
申请号：US11241877
申请日：2005-09-30
申请人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
发明人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
IPC分类号： H01L21/4763 , H01L21/3205 , H01L21/44
CPC分类号： H01L27/115 , H01L21/76838 , H01L27/11521 , H01L27/11568
摘要： A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x). Thereby, forming the bitlines (14) in direct contact to top surfaces (7) of contact structures (3) is possible without the risk of short circuits between adjacent bitlines (14).
摘要翻译：半导体产品（1）包括沿衬底表面（22）沿着第一横向（x）延伸的多个字线，并且还包括接触结构（3）以及它们之间的填充结构（4）。沿着第一方向（x），接触结构（3）和填充结构（4）以两个相应字线之间的交替顺序排列。每个接触结构（3）用于将由一个相应的沟槽隔离填充物（24）分开的两个有效区域（23）连接到相应的位线（14）。因此，第一接触结构（3）的宽度比沿着第一方向（x）的位线（14）的宽度大得多。根据本发明的实施例，接触结构（3）的锥形上部（9）成形，上部（9）的宽度明显小于接触结构（3）沿着第一方向（3）的宽度 X）。因此，形成与接触结构（3）的顶表面（7）直接接触的位线（14）是可能的，而不会在相邻位线（14）之间发生短路。

49. 发明授权

US07199002B2 Process for fabrication of a ferroelectric capacitor 失效
标题翻译：铁电电容器制造工艺
公开(公告)号：US07199002B2
公开(公告)日：2007-04-03
申请号：US10651614
申请日：2003-08-29
申请人： Karl Hornik , Rainer Bruchhaus , Nicolas Nagel
发明人： Karl Hornik , Rainer Bruchhaus , Nicolas Nagel
IPC分类号： H01L27/108
CPC分类号： H01L28/56 , H01L21/31616 , H01L21/31683
摘要： A process for the fabrication of a ferroelectric capacitor comprising depositing a layer of Ti 5 over an insulating layer 3 of Al2O3, and oxidising the Ti layer to form a TiO2 layer 7. Subsequently, a layer of PZT 9 is formed over the TiO2 layer 7. The PZT layer 9 is subjected to an annealing step in which, due to the presence of the TiO2 layer 7 it crystallises to form a layer 11 with a high degree of (111)-texture.
摘要翻译：一种用于制造铁电电容器的方法，包括在Al 2 O 3 3的绝缘层3上沉积Ti 5层，并氧化Ti层以形成TiO 然后，在TiO 2层7上形成PZT 9层.PZT层9经历退火步骤，其中由于 TiO 2层7的存在使其结晶形成具有高度（111） - 纹理的层11。

50. 发明授权

US07042037B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07042037B1
公开(公告)日：2006-05-09
申请号：US10986060
申请日：2004-11-12
申请人： Hiroshi Itokawa , Koji Yamakawa , Tohru Ozaki , Yoshinori Kumura , Takamichi Tsuchiya , Nicolas Nagel , Bum-Ki Moon , Andreas Hilliger
发明人： Hiroshi Itokawa , Koji Yamakawa , Tohru Ozaki , Yoshinori Kumura , Takamichi Tsuchiya , Nicolas Nagel , Bum-Ki Moon , Andreas Hilliger
IPC分类号： H01L31/062
CPC分类号： H01L28/55 , G11C11/22 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.
摘要翻译：公开了一种半导体器件，包括半导体衬底，设置在半导体衬底上方并包括底电极，顶电极和设置在底电极和顶电极之间的电介质膜的电容器，底电极包括含有铱，设置在电介质膜和第一导电膜之间并由贵金属膜形成的第二导电膜，设置在电介质膜和第二导电膜之间并由具有钙钛矿结构的金属氧化物膜形成的第三导电膜，以及设置在所述第一导电膜和所述第二导电膜之间并且包括金属膜和金属氧化物膜中的至少一种的防扩散膜，所述扩散防止膜防止包含在所述第一导电膜中的铱的扩散。

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