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1. 发明授权

US07714377B2 Integrated circuits and methods of manufacturing thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US07714377B2
公开(公告)日：2010-05-11
申请号：US11737617
申请日：2007-04-19
申请人： Michael Specht , Nicolas Nagel , Franz Hofmann , Thomas Mikolajick
发明人： Michael Specht , Nicolas Nagel , Franz Hofmann , Thomas Mikolajick
IPC分类号： H01L29/788
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , Y10T29/49117
摘要： Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.
摘要翻译：本发明的实施例涉及具有存储单元布置的集成电路及其制造方法。在本发明的一个实施例中，集成电路具有存储单元布置，其包括沿其纵向方向延伸的翅片结构作为第一方向，包括第一绝缘层，设置在第一绝缘层上方的第一有源区，第二绝缘层设置在所述第一有源区上方的第二有源区，设置在所述第二绝缘层上方的第二有源区，电荷存储层结构，其至少布置在所述鳍结构的至少一个侧壁上，覆盖所述第一有源区的至少一部分，并且至少第二有源区的一部分，以及设置在电荷存储层结构旁边的控制栅。

2. 发明申请

US20080259687A1 Integrated Circuits and Methods of Manufacturing Thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20080259687A1
公开(公告)日：2008-10-23
申请号：US11737617
申请日：2007-04-19
申请人： Michael Specht , Nicolas Nagel , Franz Hofmann , Thomas Mikolajick
发明人： Michael Specht , Nicolas Nagel , Franz Hofmann , Thomas Mikolajick
IPC分类号： G11C5/00 , H01R43/00
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , Y10T29/49117
摘要： Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.
摘要翻译：本发明的实施例涉及具有存储单元布置的集成电路及其制造方法。在本发明的一个实施例中，集成电路具有存储单元布置，其包括沿其纵向方向延伸的翅片结构作为第一方向，包括第一绝缘层，设置在第一绝缘层上方的第一有源区，第二绝缘层设置在所述第一有源区上方的第二有源区，设置在所述第二绝缘层上方的第二有源区，电荷存储层结构，其至少布置在所述鳍结构的至少一个侧壁上，覆盖所述第一有源区的至少一部分，并且至少第二有源区的一部分，以及设置在电荷存储层结构旁边的控制栅。

3. 发明申请

US20080073694A1 Memory cell arrangements and methods of manufacturing memory cell arrangements 有权
标题翻译：存储单元布置和制造存储单元布置的方法
公开(公告)号：US20080073694A1
公开(公告)日：2008-03-27
申请号：US11526149
申请日：2006-09-22
申请人： Josef Willer , Thomas Mikolajick , Nicolas Nagel , Michael Specht
发明人： Josef Willer , Thomas Mikolajick , Nicolas Nagel , Michael Specht
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.
摘要翻译：存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管晶体管，其中至少有一些是存储单元。电介质材料在第一存储单元串和第二存储单元串之间和之上。源极/漏极线沟槽限定在电介质材料中。源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。导电填充材料设置在源极/漏极线槽中。电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。

4. 发明授权

US07838921B2 Memory cell arrangements 有权
标题翻译：存储单元布置
公开(公告)号：US07838921B2
公开(公告)日：2010-11-23
申请号：US11526149
申请日：2006-09-22
申请人： Josef Willer , Thomas Mikolajick , Nicolas Nagel , Michael Specht
发明人： Josef Willer , Thomas Mikolajick , Nicolas Nagel , Michael Specht
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.
摘要翻译：存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管晶体管，其中至少有一些是存储单元。电介质材料在第一存储单元串和第二存储单元串之间和之上。源极/漏极线沟槽限定在电介质材料中。源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。导电填充材料设置在源极/漏极线槽中。电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。

5. 发明申请

US20080080226A1 Memory system and method of operating the memory system 审中-公开
标题翻译：内存系统和操作内存系统的方法
公开(公告)号：US20080080226A1
公开(公告)日：2008-04-03
申请号：US11526850
申请日：2006-09-25
申请人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
发明人： Thomas Mikolajick , Rainer Spielberg , Nicolas Nagel , Michael Specht , Josef Willer , Detlev Richter , Luca de Ambroggi , Andreas Taeuber
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/5614 , G11C7/1006 , G11C7/22 , G11C11/16 , G11C13/0011 , G11C13/0069 , G11C2013/0078 , G11C2207/107 , G11C2211/5641
摘要： A memory system includes a plurality of resistive memory cell fields including at least a first resistive memory cell field and a second resistive memory cell field, the first resistive memory cell field formed with a plurality of resistive memory cells storing data at a first data storage speed, the second resistive memory cell field formed with a plurality of resistive memory cells storing data at a second data storage speed lower than the first data storage speed, and a controller controlling data transfer between the plurality of resistive memory cell fields.
摘要翻译：存储器系统包括多个电阻存储单元区域，至少包括第一电阻存储单元区域和第二电阻存储单元区域，第一电阻存储单元区域形成有多个电阻存储单元，以第一数据存储速度存储数据形成有以低于第一数据存储速度的第二数据存储速度存储数据的多个电阻性存储单元形成的第二电阻性存储单元区域，以及控制器，用于控制多个电阻性存储单元区域之间的数据传输。

6. 发明申请

US20070001305A1 Method for forming a semiconductor product and semiconductor product 失效
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US20070001305A1
公开(公告)日：2007-01-04
申请号：US11172366
申请日：2005-06-30
申请人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
发明人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.
摘要翻译：半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。在其中设置有具有接触孔的第二介质层。接触孔在第一横向具有宽度。该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

7. 发明授权

US07521351B2 Method for forming a semiconductor product and semiconductor product 失效
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US07521351B2
公开(公告)日：2009-04-21
申请号：US11172366
申请日：2005-06-30
申请人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
发明人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.
摘要翻译：半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。在其中设置有具有接触孔的第二介质层。接触孔在第一横向具有宽度。该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

8. 发明申请

US20070077748A1 Method for forming a semiconductor product and semiconductor product 审中-公开
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US20070077748A1
公开(公告)日：2007-04-05
申请号：US11241877
申请日：2005-09-30
申请人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
发明人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
IPC分类号： H01L21/4763 , H01L21/3205 , H01L21/44
CPC分类号： H01L27/115 , H01L21/76838 , H01L27/11521 , H01L27/11568
摘要： A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x). Thereby, forming the bitlines (14) in direct contact to top surfaces (7) of contact structures (3) is possible without the risk of short circuits between adjacent bitlines (14).
摘要翻译：半导体产品（1）包括沿衬底表面（22）沿着第一横向（x）延伸的多个字线，并且还包括接触结构（3）以及它们之间的填充结构（4）。沿着第一方向（x），接触结构（3）和填充结构（4）以两个相应字线之间的交替顺序排列。每个接触结构（3）用于将由一个相应的沟槽隔离填充物（24）分开的两个有效区域（23）连接到相应的位线（14）。因此，第一接触结构（3）的宽度比沿着第一方向（x）的位线（14）的宽度大得多。根据本发明的实施例，接触结构（3）的锥形上部（9）成形，上部（9）的宽度明显小于接触结构（3）沿着第一方向（3）的宽度 X）。因此，形成与接触结构（3）的顶表面（7）直接接触的位线（14）是可能的，而不会在相邻位线（14）之间发生短路。

9. 发明授权

US06773986B2 Method for fabricating a semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US06773986B2
公开(公告)日：2004-08-10
申请号：US10186662
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the invention forms the capacitor devices in substantially vertically extending fashion, to, as a result, achieve a substantially three-dimensional configuration and an configuration extending into the third dimension for the capacitor devices, a contact connection of the storage capacitors being formed after the production of the storage capacitors.
摘要翻译：为了在具有存储电容器作为存储元件的半导体存储器件中实现最高可能的积分密度，根据本发明的方法以基本上垂直延伸的方式形成电容器器件，结果实现基本上三维配置和配置延伸到用于电容器器件的第三维度中，在存储电容器的生产之后形成存储电容器的接触连接。

10. 发明授权

US06704219B2 FeRAM memory and method for manufacturing it 失效
标题翻译： FeRAM存储器及其制造方法
公开(公告)号：US06704219B2
公开(公告)日：2004-03-09
申请号：US10186645
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , H01L28/86
摘要： To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.
摘要翻译：为了以特别节省空间的方式制造FeRAM存储器，因此增加存储密度，制造方法形成用作存储元件的多个电容器器件中的至少一些，其中多个单独的电容器与一个并联连接另一个。各个电容器具有不同强制电压的铁电或对称电介质区域，使得每个单独的电容器存在多个存储状态。

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