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1. 发明申请

US20090251968A1 Integrated circuit having a base structure and a nanostructure 审中-公开
标题翻译：具有基底结构和纳米结构的集成电路
公开(公告)号：US20090251968A1
公开(公告)日：2009-10-08
申请号：US12099522
申请日：2008-04-08
申请人： Christoph Andreas Kleint , Josef Willer
发明人： Christoph Andreas Kleint , Josef Willer
IPC分类号： H01L21/00 , G11C16/04
CPC分类号： H01L27/11578 , H01L27/11582
摘要： In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure.
摘要翻译：在一个实施例中，集成电路可以包括金属导电结构，具有晶体取向的基底结构，与金属导电结构相邻的基底结构，以及设置在基底结构上的纳米结构，纳米结构具有基本上相同的晶体取向作为基础结构。

2. 发明申请

US20080237738A1 Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell arrangement; memory module 审中-公开
标题翻译：集成电路，电池，电池布置，集成电路的制造方法，电池装置的制造方法。内存模块
公开(公告)号：US20080237738A1
公开(公告)日：2008-10-02
申请号：US11728970
申请日：2007-03-27
申请人： Christoph Andreas Kleint , Dirk Manger , Nicolas Nagel , Andreas Taeuber
发明人： Christoph Andreas Kleint , Dirk Manger , Nicolas Nagel , Andreas Taeuber
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/743 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： The present invention relates generally to integrated circuits, a cell, a cell arrangement, a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement and a memory module. In an embodiment of the invention, an integrated circuit having a cell is provided. The cell includes a first source/drain region, a second source/drain region, an active region between the first source/drain region and the second source/drain region, a gate insulating region disposed above the active region, a gate region disposed above the gate insulating region, and at least one metal structure below the first source/drain region or the second source/drain region.
摘要翻译：本发明一般涉及集成电路，单元，单元布置，集成电路的制造方法，单元布置的制造方法和存储器模块。在本发明的实施例中，提供了具有单元的集成电路。电池包括第一源极/漏极区域，第二源极/漏极区域，第一源极/漏极区域和第二源极/漏极区域之间的有源区域，设置在有源区域上方的栅极绝缘区域，栅极绝缘区域以及在第一源极/漏极区域或第二源极/漏极区域下方的至少一个金属结构。

3. 发明授权

US07144776B1 Charge-trapping memory device 失效
标题翻译：电荷俘获存储器件
公开(公告)号：US07144776B1
公开(公告)日：2006-12-05
申请号：US11141254
申请日：2005-05-31
申请人： Ricardo Pablo Mikalo , Erwin Schroer , Günther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Andreas Kleint
发明人： Ricardo Pablo Mikalo , Erwin Schroer , Günther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Andreas Kleint
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.
摘要翻译：氧化区域布置在半导体材料的衬底和氮化物衬垫之间，其覆盖存储单元阵列的字线堆叠和衬底的中间区域，并且被提供以将氮化物衬垫与衬底和存储器层序列分离的电介质材料，用于电荷捕获。氮化物衬垫在形成用于外围区域的侧壁间隔物中用作蚀刻停止层，以产生寻址电路的晶体管的源极/漏极结。

4. 发明授权

US07416976B2 Method of forming contacts using auxiliary structures 有权
标题翻译：使用辅助结构形成触点的方法
公开(公告)号：US07416976B2
公开(公告)日：2008-08-26
申请号：US11217122
申请日：2005-08-31
申请人： Josef Willer , Patrick Haibach , Christoph Andreas Kleint , Nicolas Nagel
发明人： Josef Willer , Patrick Haibach , Christoph Andreas Kleint , Nicolas Nagel
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.
摘要翻译：半导体产品包括具有基板表面的基板。多个字线被布置成彼此间隔一定距离并沿着第一方向延伸。在字线之间提供多个导电接触结构。该产品还包括多个填充结构。每个填充结构彼此分开布置在两个相应字线之间的两个相应的接触结构。两个相应的接触结构在第一方向上彼此间隔一定距离。在优选实施例中，接触结构具有设置在离基板表面一定距离处并且延伸到基板表面的顶侧。衬底表面处的接触结构具有沿着第一方向的宽度，该宽度大于沿着第一方向的接触结构的顶侧宽度。

5. 发明授权

US07405441B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07405441B2
公开(公告)日：2008-07-29
申请号：US11078647
申请日：2005-03-11
申请人： Joachim Deppe , Mathias Krause , Christoph Andreas Kleint , Christoph Ludwig , Jens-Uwe Sachse , Günther Wein
发明人： Joachim Deppe , Mathias Krause , Christoph Andreas Kleint , Christoph Ludwig , Jens-Uwe Sachse , Günther Wein
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/792
摘要： A non-volatile semiconductor memory (30) comprising a semiconductor substrate (1) and a plurality of memory cells (19) and methods for manufacturing such a memory is provided. Each memory cell (19) comprises a charge-trapping element (5), a gate stack (20), nitride spacers (10) and electrically insulating elements (21). The charge-trapping element (5) is arranged on the semiconductor substrate (1) and comprises a nitride layer (3) sandwiched between a bottom oxide layer (2) and a top oxide layer (4), the charge-trapping element (5) having two lateral sidewalls (24) opposed to one another. The gate stack (20) is arranged on top of the charge-trapping element (5), the gate stack having two lateral sidewalls (25) opposing one another. The electrically insulating elements (21) are disposed at opposing sidewalls (24) of the charge-trapping element (5) and cover the sidewalls (24) of the charge-trapping element (5). The nitride spacers (10) cover the electrically insulating elements (21) and are arranged on opposing sidewalls (25) of the gate stack (20) and on the electrically insulating elements (21).
摘要翻译：提供了包括半导体衬底（1）和多个存储单元（19）的非易失性半导体存储器（30）和用于制造这种存储器的方法。每个存储单元（19）包括电荷捕获元件（5），栅极堆叠（20），氮化物间隔物（10）和电绝缘元件（21）。电荷捕获元件（5）设置在半导体衬底（1）上并且包括夹在底部氧化物层（2）和顶部氧化物层（4）之间的氮化物层（3），电荷俘获元件（5））具有彼此相对的两个侧壁（24）。栅极堆叠（20）布置在电荷捕获元件（5）的顶部，栅极堆叠具有彼此相对的两个侧壁（25）。电绝缘元件（21）设置在电荷捕获元件（5）的相对侧壁（24）处并覆盖电荷捕获元件（5）的侧壁（24）。氮化物间隔物（10）覆盖电绝缘元件（21）并且布置在栅极堆叠（20）的相对侧壁（25）上以及电绝缘元件（21）上。

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