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1. 发明申请

US20070077748A1 Method for forming a semiconductor product and semiconductor product 审中-公开
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US20070077748A1
公开(公告)日：2007-04-05
申请号：US11241877
申请日：2005-09-30
申请人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
发明人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
IPC分类号： H01L21/4763 , H01L21/3205 , H01L21/44
CPC分类号： H01L27/115 , H01L21/76838 , H01L27/11521 , H01L27/11568
摘要： A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x). Thereby, forming the bitlines (14) in direct contact to top surfaces (7) of contact structures (3) is possible without the risk of short circuits between adjacent bitlines (14).
摘要翻译：半导体产品（1）包括沿衬底表面（22）沿着第一横向（x）延伸的多个字线，并且还包括接触结构（3）以及它们之间的填充结构（4）。沿着第一方向（x），接触结构（3）和填充结构（4）以两个相应字线之间的交替顺序排列。每个接触结构（3）用于将由一个相应的沟槽隔离填充物（24）分开的两个有效区域（23）连接到相应的位线（14）。因此，第一接触结构（3）的宽度比沿着第一方向（x）的位线（14）的宽度大得多。根据本发明的实施例，接触结构（3）的锥形上部（9）成形，上部（9）的宽度明显小于接触结构（3）沿着第一方向（3）的宽度 X）。因此，形成与接触结构（3）的顶表面（7）直接接触的位线（14）是可能的，而不会在相邻位线（14）之间发生短路。

2. 发明申请

US20070001305A1 Method for forming a semiconductor product and semiconductor product 失效
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US20070001305A1
公开(公告)日：2007-01-04
申请号：US11172366
申请日：2005-06-30
申请人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
发明人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.
摘要翻译：半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。在其中设置有具有接触孔的第二介质层。接触孔在第一横向具有宽度。该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

3. 发明授权

US07521351B2 Method for forming a semiconductor product and semiconductor product 失效
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US07521351B2
公开(公告)日：2009-04-21
申请号：US11172366
申请日：2005-06-30
申请人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
发明人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.
摘要翻译：半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。在其中设置有具有接触孔的第二介质层。接触孔在第一横向具有宽度。该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

4. 发明授权

US07368350B2 Memory cell arrays and methods for producing memory cell arrays 有权
标题翻译：用于产生存储单元阵列的存储单元阵列和方法
公开(公告)号：US07368350B2
公开(公告)日：2008-05-06
申请号：US11313247
申请日：2005-12-20
申请人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
发明人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/76831 , H01L21/76888 , H01L21/76897 , H01L27/11568
摘要： A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.
摘要翻译：公开了一种用于制造堆叠的非易失性存储单元和非易失性存储单元阵列的方法。提供半导体晶片，其具有沉积在半导体晶片的表面上的电荷捕获层和导电层。在导电层的顶部使用掩模层，形成接触填充材料沉积到其中的接触孔。另外的导电层沉积在半导体晶片的表面上并被图案化以形成字线。接触填充材料使用接触孔与接触填充材料作为着陆垫连接到接触塞。

5. 发明申请

US20070141799A1 Memory cell arrays and methods for producing memory cell arrays 有权
标题翻译：用于产生存储单元阵列的存储单元阵列和方法
公开(公告)号：US20070141799A1
公开(公告)日：2007-06-21
申请号：US11313247
申请日：2005-12-20
申请人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
发明人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L21/76831 , H01L21/76888 , H01L21/76897 , H01L27/11568
摘要： A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.
摘要翻译：公开了一种用于制造堆叠的非易失性存储单元和非易失性存储单元阵列的方法。提供半导体晶片，其具有沉积在半导体晶片的表面上的电荷捕获层和导电层。在导电层的顶部使用掩模层，形成接触填充材料沉积到其中的接触孔。另外的导电层沉积在半导体晶片的表面上并被图案化以形成字线。接触填充材料使用接触孔与接触填充材料作为着陆垫连接到接触塞。

6. 发明申请

US20070057318A1 Semiconductor memory device and method of production 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070057318A1
公开(公告)日：2007-03-15
申请号：US11228036
申请日：2005-09-15
申请人： Lars Bach , Dominik Olligs , Torsten Mueller , Veronika Polei
发明人： Lars Bach , Dominik Olligs , Torsten Mueller , Veronika Polei
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7923 , H01L27/11568 , H01L29/40117 , H01L29/42352
摘要： A semiconductor substrate is provided with a recess. A memory layer or memory layer sequence is applied to sidewalls and the bottom of the recess. The memory layer is formed into two separate portions at opposite sidewalls of the recess either by reducing the memory layer to sidewall spacers or by forming sidewall spacers and removing portions of the memory layer that are not covered by the spacers. A gate electrode is applied into the recess, and source/drain regions are formed by an implantation of doping atoms adjacent to the sidewalls of the recess and the remaining portions of the memory layer. The memory layer can especially be a dielectric material suitable for charge-trapping.
摘要翻译：半导体衬底设置有凹部。存储层或存储器层序列被施加到凹槽的侧壁和底部。存储层通过将存储层减小到侧壁间隔物或通过形成侧壁间隔物和去除未被间隔物覆盖的存储层的部分而在凹槽的相对侧壁处形成两个分开的部分。栅电极被施加到凹槽中，并且通过注入与凹槽的侧壁和存储层的其余部分相邻的掺杂原子来形成源/漏区。存储层可以特别地是适用于电荷俘获的电介质材料。

7. 发明授权

US07589019B2 Memory cell array and method of forming a memory cell array 有权
标题翻译：存储单元阵列和形成存储单元阵列的方法
公开(公告)号：US07589019B2
公开(公告)日：2009-09-15
申请号：US11443432
申请日：2006-05-31
申请人： Dominik Olligs , Veronika Polei
发明人： Dominik Olligs , Veronika Polei
IPC分类号： H01L21/44 , H01L29/40
CPC分类号： H01L27/115
摘要： A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partially formed in a semiconductor substrate and are accessible by addressing at least a corresponding one of the first conductive lines and at least a corresponding one of the second conductive lines. The memory cell array further includes a plurality of supporting lines, where the supporting lines have a pitch Mp and are disposed above the first and second conductive lines, and a plurality of supporting contacts. The first conductive lines are connected with corresponding ones of the supporting lines via the supporting contacts, and Mp is larger than Bp.
摘要翻译：存储单元阵列包括沿第一方向延伸的多条第一导线，其中第一导线具有间距Bp，多条第二导线和多个存储单元。每个存储单元至少部分地形成在半导体衬底中，并且可以通过寻址至少对应的一个第一导线和至少相应的一个第二导线。存储单元阵列还包括多个支撑线，其中支撑线具有间距Mp并且设置在第一和第二导线上方，以及多个支撑触点。第一导线通过支撑触点与相应的支撑线连接，Mp大于Bp。

8. 发明申请

US20070278546A1 Memory cell array and method of forming a memory cell array 有权
标题翻译：存储单元阵列和形成存储单元阵列的方法
公开(公告)号：US20070278546A1
公开(公告)日：2007-12-06
申请号：US11443432
申请日：2006-05-31
申请人： Dominik Olligs , Veronika Polei
发明人： Dominik Olligs , Veronika Polei
IPC分类号： H01L29/94
CPC分类号： H01L27/115
摘要： A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partially formed in a semiconductor substrate and are accessible by addressing at least a corresponding one of the first conductive lines and at least a corresponding one of the second conductive lines. The memory cell array further includes a plurality of supporting lines, where the supporting lines have a pitch Mp and are disposed above the first and second conductive lines, and a plurality of supporting contacts. The first conductive lines are connected with corresponding ones of the supporting lines via the supporting contacts, and Mp is larger than Bp.
摘要翻译：存储单元阵列包括沿第一方向延伸的多条第一导线，其中第一导线具有间距Bp，多条第二导线和多个存储单元。每个存储单元至少部分地形成在半导体衬底中，并且可以通过寻址至少对应的一个第一导线和至少相应的一个第二导线。存储单元阵列还包括多个支撑线，其中支撑线具有间距Mp并且设置在第一和第二导线上方，以及多个支撑触点。第一导线通过支撑触点与相应的支撑线连接，Mp大于Bp。

9. 发明申请

US20070200149A1 Semiconductor device and method of production 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070200149A1
公开(公告)日：2007-08-30
申请号：US11364586
申请日：2006-02-28
申请人： Veronika Polei , Dominik Olligs
发明人： Veronika Polei , Dominik Olligs
IPC分类号： H01L29/80
CPC分类号： H01L21/0206 , H01L21/28061 , H01L21/32139 , H01L29/4941
摘要： A layer sequence with lateral boundaries, especially a gate electrode stack, comprises a cover layer between a metal layer and a top layer that is provided as a hardmask. The cover layer, which is preferably polysilicon, enables the application of a cleaning agent to remove a resist layer, clean the hardmask and remove deposits of the material of the top layer produced in the structuring of the hardmask, before the layer sequence is structured using the hardmask. The cover layer protects the metal layer, which could otherwise be damaged by the cleaning agent.
摘要翻译：具有横向边界的层序列，特别是栅极电极堆叠，包括在作为硬掩模提供的金属层和顶层之间的覆盖层。优选多晶硅的覆盖层能够在层序列结构化之前使用清洁剂去除抗蚀剂层，清洁硬掩模并去除硬质掩模的结构中产生的顶层材料的沉积物硬掩模覆盖层保护金属层，否则可能由清洁剂损坏。

10. 发明授权

US07026220B1 Method for production of charge-trapping memory devices 失效
标题翻译：电荷俘获存储器件的制造方法
公开(公告)号：US07026220B1
公开(公告)日：2006-04-11
申请号：US11006484
申请日：2004-12-07
申请人： Georg Tempel , Elard Stein von Kamienski , Stephan Riedel , Veronika Polei , Roland Haberkern , Roman Knoefler
发明人： Georg Tempel , Elard Stein von Kamienski , Stephan Riedel , Veronika Polei , Roland Haberkern , Roman Knoefler
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.
摘要翻译：该方法旨在改善面向掩埋位线区域的边缘处的存储层的电荷限制。在限制层之间的存储层沉积和用于位线和源/漏区的掺杂剂的注入之后，发生半导体材料的氧化以形成上位线隔离区。通过该方法，在相同的氧化步骤中在存储层的边缘产生附加的氧化物区域。可以将硅层沉积并还原成侧壁间隔物，其随后被氧化; 或凹槽蚀刻到存储层中，随后填充半导体氧化物。

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