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41. 发明申请

US20120248508A1 FORMING BORDERLESS CONTACT FOR TRANSISTORS IN A REPLACEMENT METAL GATE PROCESS 有权
标题翻译：在替代金属门过程中形成晶体管的无边界接触
公开(公告)号：US20120248508A1
公开(公告)日：2012-10-04
申请号：US13073151
申请日：2011-03-28
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/41733 , H01L29/41783 , H01L29/4966 , H01L29/6653 , H01L29/66553
摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.
摘要翻译：本发明的实施例提供一种形成半导体结构的方法。该方法包括在电介质层内形成开口，介电层形成在衬底的顶部，并且该开口暴露衬底中晶体管的沟道区; 沉积衬套开口并覆盖通道区域的功函数层; 形成覆盖所述功函数层的第一部分的栅极导体，所述功函数层的所述第一部分位于所述沟道区的顶部; 并且去除所述功函数层的第二部分，所述功函数层的包围所述功函数层的第一部分的所述第二部分，其中所述功函数层的所述第二部分的去除使所述功函数层的第一部分绝缘工作功能层的工作功能层。

42. 发明申请

US20120187566A1 AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION 有权
标题翻译：空气介质用于分层蚀刻线和通过金属化
公开(公告)号：US20120187566A1
公开(公告)日：2012-07-26
申请号：US13013108
申请日：2011-01-25
申请人： David V. Horak , Elbert Huang , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Elbert Huang , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/522 , H01L21/76802 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.
摘要翻译：公开了一种方法和结构，其中可以形成具有位于最容易受电容耦合的区域中的有效气隙的多个互连层。该方法包括提供导电特征层，所述层包括设置在基底上并彼此隔开小于或等于有效距离的至少两个线构件，以及至少一个这样的线构件，其还具有延伸的通孔构件离开基板，沉积不良共形介电涂层以在这些线构件之间形成气隙，并露出通孔的顶端。

43. 发明授权

US08198700B2 Deep well structures with single depth shallow trench isolation regions 有权
标题翻译：深井结构，具有单深度浅沟槽隔离区
公开(公告)号：US08198700B2
公开(公告)日：2012-06-12
申请号：US12691196
申请日：2010-01-21
申请人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
发明人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
IPC分类号： H01L27/092
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/0921
摘要： A semiconductor device structure includes a first type region and a second type region defined in a substrate, the first type region and second type region separated by one or more inter-well shallow trench isolation (STI) structures. At least one of the first type region and the second type region has one or more intra-well STI structures formed therein for isolating semiconductor devices formed within a same polarity well. The inter-well STI structures are formed at a substantially same depth with respect to the intra-well STI structures. A main well region is formed such that a bottom of the main well region is disposed above a bottom of the inter-well and intra-well STI features. One or more deep well regions couple the main well regions otherwise isolated by the intra-well STI structures, wherein the deep well regions are spaced away from the inter-well STI structures.
摘要翻译：半导体器件结构包括限定在衬底中的第一类型区域和第二类型区域，第一类型区域和第二类型区域被一个或多个阱间浅沟槽隔离（STI）结构隔开。第一类型区域和第二类型区域中的至少一个具有形成在其中的一个或多个井内STI结构，用于隔离在相同极性内形成的半导体器件。井间STI结构相对于井内STI结构形成在基本相同的深度。形成主阱区域，使得主阱区域的底部设置在井间和井内STI特征的底部之上。一个或多个深井区域连接主井区域，否则由井内STI结构隔离，其中深井区域与井间STI结构间隔开。

44. 发明申请

US20120086128A1 BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS 有权
标题翻译：无边界连接线结构自上而下
公开(公告)号：US20120086128A1
公开(公告)日：2012-04-12
申请号：US12899911
申请日：2010-10-07
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/528 , H01L21/76885 , H01L21/76897 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
摘要翻译：金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准。沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。

45. 发明授权

US08138100B2 Microelectronic structure by selective deposition 有权
标题翻译：微电子结构通过选择性沉积
公开(公告)号：US08138100B2
公开(公告)日：2012-03-20
申请号：US12273908
申请日：2008-11-19
申请人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795 , H01L29/78645
摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.
摘要翻译： finFET结构包括位于衬底上的半导体鳍片。栅电极穿过半导体鳍片。栅电极具有邻接其侧壁的间隔层。间隔层不完全覆盖半导体鳍片的侧壁。栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上，而不是在衬底的邻接表面上，使得间隔层不完全覆盖半导体的侧壁鳍。可以使用侧向生长方法制造其它微电子结构。

46. 发明申请

US20110266621A1 FIELD EFFECT TRANSISTOR 有权
标题翻译：场效应晶体管
公开(公告)号：US20110266621A1
公开(公告)日：2011-11-03
申请号：US13179635
申请日：2011-07-11
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/78 , H01L29/786
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
摘要翻译：晶体管。晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

47. 发明申请

US20110175190A1 DEEP WELL STRUCTURES WITH SINGLE DEPTH SHALLOW TRENCH ISOLATION REGIONS 有权
标题翻译：深深的结构与单深深浅的分离分离区域
公开(公告)号：US20110175190A1
公开(公告)日：2011-07-21
申请号：US12691196
申请日：2010-01-21
申请人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
发明人： Charles W. Koburger, III , Peter Zeitzoff , Mariko Takayanagi
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/0921
摘要： A semiconductor device structure includes a first type region and a second type region defined in a substrate, the first type region and second type region separated by one or more inter-well shallow trench isolation (STI) structures. At least one of the first type region and the second type region has one or more intra-well STI structures formed therein for isolating semiconductor devices formed within a same polarity well. The inter-well STI structures are formed at a substantially same depth with respect to the intra-well STI structures. A main well region is formed such that a bottom of the main well region is disposed above a bottom of the inter-well and intra-well STI features. One or more deep well regions couple the main well regions otherwise isolated by the intra-well STI structures, wherein the deep well regions are spaced away from the inter-well STI structures.
摘要翻译：半导体器件结构包括限定在衬底中的第一类型区域和第二类型区域，第一类型区域和第二类型区域被一个或多个阱间浅沟槽隔离（STI）结构隔开。第一类型区域和第二类型区域中的至少一个具有形成在其中的一个或多个井内STI结构，用于隔离在相同极性内形成的半导体器件。井间STI结构相对于井内STI结构形成在基本相同的深度。形成主阱区域，使得主阱区域的底部设置在井间和井内STI特征的底部之上。一个或多个深井区域连接主井区域，否则由井内STI结构隔离，其中深井区域与井间STI结构间隔开。

48. 发明申请

US20110027951A1 SHARED GATE FOR CONVENTIONAL PLANAR DEVICE AND HORIZONTAL CNT 有权
标题翻译：常规平面设备和水平CNT的共享门
公开(公告)号：US20110027951A1
公开(公告)日：2011-02-03
申请号：US12902944
申请日：2010-10-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

49. 发明授权

US07652334B2 Shallow trench isolation formation 有权
标题翻译：浅沟隔离形成
公开(公告)号：US07652334B2
公开(公告)日：2010-01-26
申请号：US11866471
申请日：2007-10-03
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/72
CPC分类号： H01L21/02164 , H01L21/0214 , H01L21/02282 , H01L21/3143 , H01L21/3147 , H01L21/316 , H01L21/76224 , H01L21/823878
摘要： A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.
摘要翻译：一种用于形成半导体结构的方法和结构。提供半导体衬底。在半导体衬底内形成沟槽。第一层电绝缘材料形成在沟槽内。去除第一层电绝缘材料的第一部分和第二部分。选择性地在第一层上生长第二层电绝缘材料，该第一层包括去除的第一部分和被去除的第二部分。

50. 发明授权

US07521808B2 Wiring paterns formed by selective metal plating 失效
标题翻译：通过选择性金属电镀形成的布线
公开(公告)号：US07521808B2
公开(公告)日：2009-04-21
申请号：US11745610
申请日：2007-05-08
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L28/528
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/7682 , H01L21/76837 , H01L21/76852 , H01L21/76862 , H01L21/76871 , H01L21/76874 , H01L23/5283 , H01L23/53209 , H01L2221/1089 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.
摘要翻译：使用图案结构（心轴）并激活结构的侧壁的方法形成导电侧壁间隔结构。金属离子附着在结构的侧壁上，这些金属离子被还原成晶种。然后对结构进行修整，并且种子材料被电镀以在结构的侧壁上形成布线。

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